Lexicon 200, Service Manual, Page: 39 / 90

Lexicon
6-3
AK4528 CODEC
The AKM CODEC AK4528 is a high performance 24-bit A/D-D/A device which performs anti-alias filtering,
analog to digital conversion, digital to analog conversion, and digital 15/50uS de-emphasis. Although it
supports sampling rates up to 96kHz, the MPX200 only supports 44.1kHz sampling.
The ADC inputs are fully differential. The input signal range is scaled to the VREF pin. Nominally, this range
is defined as (0.56 x VREF) Volts peak to peak. With VREF equal to 5V and a DC input offset voltage of
2.9V, the output code of the ADC is 0x7FFFFF positive full scale and 0x800000 negative full scale. The
data is in 2’s complement form. The input is sampled at 64fs (2.8224 MHz with fs = 44.1kHz).
Serial data is clocked in on the rising edge of the bit clock and is aligned with the second bit clock following
the leading edge of each transition in the LRCLK (FS). This alignment is determined by setting the serial
data interface pins to support the I2S format. The Lexichip3 receive port (SDIN0) is configured to support
this format.
During power down, the ADC, DAC, digital filters, and control registers are reset by signal PWR_DWN/.
This is an active low signal and is provided by the Lexichip 3. The CODEC is brought out of power down
mode when the clock signals LEX_256FS, LEX_FS/, and LEX_64FS/ are stable. It these clocks are not
present, then the CODEC is placed back into power down mode. R99 provides a weak pull-down for
PWR_DWN/.
During power down (PDN = 0), the ADC, DAC, digital filters, and control registers are reset. Upon power up
(PDN = 1), the ADC initializes after a period of 516/fs. The DAC initializes after a period of 512/fs.
The DAC uses advanced multi-bit architecture and is configured to support the I2S format. The DAC runs
from a 256fs MC. The Lexichip3 generates this. Data is clocked in on the rising edge of the 64fs clock and
is aligned with the second bit clock following the leading edge of each transition of the fs clock. This
alignment is determined by programming the Lexichip3 Serial Transmit Port (SDOUT0) to support I2S.
Digital de-emphasis is hardwired for 44.1kHz support. De-emphasis may be turned on or off by toggling the
DEM0 pin either 1 (De-emphasis is off) or a 0 (De-emphasis is on). The XD9 port of the Lexichip3 is
programmed to activate or de-activate digital de-emphasis.
C43 and C44 provide power supply de-coupling of the analog supply line and voltage reference of the
AK4528 while C38 de-couples the digital supply line and output buffer supply pins. R46 DC couples the
analog and digital supplies together while providing a measure of isolation of digital switching currents from
leaking back into the analog supply.
C39 and C40 de-couple the VCOM pin of the CODEC. This pin is the bias voltage of the ADC inputs and
the DAC outputs; this voltage is equal to VA/2.
Differential to Single-Ended Output Amplifiers
The analog outputs of the CODEC are full differential with a full-scale swing of (0.54 x VREF) volts peak to
peak. This output signal is centered on 2.5V. Both sections of dual op amp U4 are configured as unity gain
second order low pass filters with an Fc = 93.2kHz. These filters provide summing of the differential signals
for each channel into single-ended signals. R30, R31, R32, R34, R35, R36, C30, C31, and C32 form the
low pass filter for the right channel (OUT_RIGHT) while R38, R39, R40, R42, R43, R44, C35, C36, and C37
comprise the low pass filter for the left channel (OUT_LEFT). Both signals are referred back to page 1 to
the Output and Mute circuitry. Reg/-5V rails power these op amps.
Sheet 3
This sheet shows the S/PDIF input and output circuitry, the Digital Audio Receiver, Program Select rotary
encoder, and the glue logic necessary to implement these functions. The S/PDIF IO is implemented in a
dual RCA phono jack.