Lexicon 200, Service Manual

Page: 45 / 90

Lexicon
6-9
enables must be pulled high and the Z80 must be fed clocks to allow the resistors to work as designed.
Proper initialization of the system is dependent on the static state of the data bus on power up. The PLL
TEST Pins are diode clamped by D4 to RESET/. This ensures that the PLL is held in an inactive state until
the reset cycle ends. R68, R76, and C67 form a reference network for the PLL. R73 and R74 provide weak
pull-ups for SP_MASTER/ and SPDIF_OUT respectively. R92 and R100 provide weak pull-downs for
MUTE/ and DE_EMPH/ respectively. These pull-down components ensure that these signals default to their
active states during power up. Resistors R69, R70, R71, and R77 provide RFI protection by slowing down
the edge rates of LEX_FS/, D/A_DATA, LEX_64FS/, and LEX_256FS respectively. R72 is a provision for
further RFI protection. Currently all that is required is for this component to be a 0-ohm resistor. R75
provides a DC coupled power source to the internal PLL on the Lexichip3. C68 and C69 de-couple this
supply line.
Audio Memory
The audio memory for the Lexichip3 is provided by 1Mx16 DRAM (U17). However, the MPX200 only uses 8
of the available 16 data bits, with the most significant byte pulled up by R114-R121. Effectively this DRAM
is being used as a 1Mx8 device. Note that all address decoding (RAM_EN/, ROM_EN/, etc.) is done within
the Lexichip3. That is the primary reason the Z80 cannot function if the Lexichip3 is improperly initialized at
the rising edge of RESET/. The address bus and memory control signals provided by the Lexichip3 are
series terminated by resistors R93 through R98 and R101 through R107. This is done to provide RFI
protection. Since the most active signals on this bus are LEX_A0 and LEX_A1, these are the ones that will
cause the most emission, therefore R93 and R101 are set to 180 ohms; this value effectively slows down
the edge rates of these two signals. The remaining bus signals (LEX_A[2:9]) are less active and therefore
do not require edge rate reduction; R94, R96 through R98, R102, R105 and R106 are set to 0 ohms.
Control signals CAS/, RAS/ and WE/ require edge rate reduction due to their high level of activity.
Therefore, R95, R103, and R104 are 180 ohms.
Master Clock Generator
Y1, C76, C77, and R91 comprise the master clock generator. Signal LEX_256FS is equal to the frequency
generated here (11.2896MHz). Pins 74 and 75 on the Lexichip3 are essentially the output and input of a
CMOS buffer, respectively.
Sheet 7
This sheet shows the power supply scheme used in the MPX200. It includes the circuitry used to derive
+10VUN, +5VD, +5VA, +3.3VD, -10VUN, and -5VA as well as the rectifier circuit coming off the power
transformer secondary. Bypass capacitors C65, C70, C75, C78-C82, C87, C90, C92, C95-C99, C105-
C107, C113-C115, and C117 are distributed evenly throughout the PCB and provide Digital Power de-
coupling. C4, C14, C19, C33, and C55 are distributed evenly throughout the analog section of the PCB and
provide power supply de-coupling of the –5VA line. C3, C15, C18, C34, and C54 are distributed evenly
throughout the analog section of the PCB and provide power supply de-coupling of the +5VA line.
+10VUN and -10VUN
+10VUN is derived from the half wave rectified voltage off of the transformer. Q2, R56, R57, C58, and C60
form a capacitance multiplier. The value of C60 is effectively multiplied by the HFE of Q2, thereby providing
an ultra-clean and stable ripple filter and a large reservoir for charge.
Q1, R54, R55, C57 and C59 provide filtering and reserve in a similar manner for the -10VUN supply.
+5VD
U25, D11, and C131 provide a +5 Volt regulated supply for the entire digital domain in the system. Current
draw through this device is very close to the limit of U25, so a heatsink must always be in place on this
device, especially if the boards are powered up outside of the enclosure. Otherwise U25 will quickly go into
thermal shutdown.