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CrossLink-NX PCIe Bridge Board Basic Demo

User Guide

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FPGA-UG-02145-1.0

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Summary of Contents for CrossLink-NX PCIe

Page 1: ...CrossLink NX PCIe Bridge Board Basic Demo User Guide FPGA UG 02145 1 0 December 2021...

Page 2: ...S with all faults and associated risk the responsibility entirely of the Buyer Buyer shall not rely on any data and performance specifications or parameters provided herein Products sold by Lattice ha...

Page 3: ...Setup and Installation for Windows 14 3 2 2 Software Setup for Linux 27 4 Demo Design Overview 30 4 1 Theory of Operation 30 4 2 FPGA Design 31 4 2 1 PCIe Hard IP 32 4 2 2 BAR RAM 32 4 2 3 Display Con...

Page 4: ...18 Figure 3 19 Update Driver Menu in Device Manager 19 Figure 3 20 Update Driver Options 19 Figure 3 21 Browse the Driver for Device 20 Figure 3 22 Windows Security in Device Manager 20 Figure 3 23 Dr...

Page 5: ...product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA UG 02145 1 0 5 Tables Table 3 1 J...

Page 6: ...their respective holders The specifications and information herein are subject to change without notice 6 FPGA UG 02145 1 0 Acronyms in This Document A list of acronyms used in this document Acronym...

Page 7: ...demos discussed in this document include the PCI Express Basic Demo and PCI Express Memory Access Demo 1 1 Learning Objectives After completing the steps in this guide you will be able to perform the...

Page 8: ...o software a computer with a PCI Express 16 8 4 or 1 slot is required The computer must also have a USB port and be able to run the Lattice Radiant Software All other hardware and drivers are included...

Page 9: ...the jumpers listed in Table 3 1 If this is the first time the board is used the jumpers should be in the indicated configuration Table 3 1 Jumper Configuration Jumper Checklist Configuration J11 J18 C...

Page 10: ...osition to receive power from the PCIe slot If external 12 V power is provided then SW2 should be in the down position to receive power from the external 12 V connection Connect the board to the PC ru...

Page 11: ...ange without notice FPGA UG 02145 1 0 11 4 The main interface opens as shown in Figure 3 4 Figure 3 4 Radiant Programmer Window 5 If the Programmer settings do not match the settings shown in Figure 3...

Page 12: ...0 Figure 3 6 Device Properties Window for SPI Flash Programming 4 Select the settings as shown in Figure 3 6 5 Click the Programming button from the menu bar shown in Figure 3 7 to start programming F...

Page 13: ...tions and information herein are subject to change without notice FPGA UG 02145 1 0 13 3 1 3 Status LED The three status LEDs are shown in Figure 3 9 1 2 3 Figure 3 9 Status LED The description of eac...

Page 14: ...tion provides the procedure for installing software onto the host machine 3 2 1 Software Setup and Installation for Windows Before installing the driver driver signature enforcement should be disabled...

Page 15: ...1 2 Disabling Driver Signature Enforcement Temporarily To disable the driver signature enforcement temporarily on Windows 10 Note if Driver Signature Enforcement is already disabled skip this section...

Page 16: ...nter to restart Figure 3 15 Restarting Windows 8 After restarting select Option 7 to disable driver signature verification 3 2 1 3 Driver Installation There are two procedures to install the device dr...

Page 17: ...pective holders The specifications and information herein are subject to change without notice FPGA UG 02145 1 0 17 Figure 3 16 Device Manager 2 Right click the device and select Properties as shown i...

Page 18: ...demarks patents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and i...

Page 19: ...rand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA UG 02145 1 0 19 4 Right cl...

Page 20: ...re trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice 20 FPGA UG 02145 1 0 6 Browse for the Basic Demo devic...

Page 21: ...tered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA UG 02145 1 0 21 8 If the driver is installed successfully a message is...

Page 22: ...ing the installation of the user interface as described in the following section The Installer provides a standard packaging format for applications and a standard method for customizing the applicati...

Page 23: ...names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA UG 02145 1 0 23 4 Provide the location whe...

Page 24: ...product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice 24 FPGA UG 02145 1 0 6 Installation of...

Page 25: ...ir respective holders The specifications and information herein are subject to change without notice FPGA UG 02145 1 0 25 8 The device driver installation wizard opens Click Next Figure 3 31 Device Dr...

Page 26: ...emarks patents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and in...

Page 27: ...d trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA UG 02145 1 0 27 3 2 2 Software Setup for Linux 3 2 2 1 Supported Operating...

Page 28: ...wing commands on a terminal to install the required packages sudo apt update sudo apt install build essential sudo apt install flex 3 2 2 4 Manual Setup and Installation Before installing the driver t...

Page 29: ...2 Run the commnd below sudo insmod lattice_main ko 3 To launch the user interface application go to the app_src gui deploy directory and run the command below sudo PCIe_Test_App sh 3 2 2 5 Automatic S...

Page 30: ...board The PCIe IP present in the Lattice FPGA on the CL NX PCIe Bridge Board acts as a PCIe endpoint occupying certain ranges of PCI memory space When the PC boots the BIOS and OS probe the PCI Expre...

Page 31: ...ead write PCIe Bus driver for Lattice Endpoint User Interface Application Protocol Library BAR Memory Driver PCIe Bus Driver Figure 4 2 PCIe Basic Demo SW Design PCIe hard IP is used on the FPGA side...

Page 32: ...ping scrambling descrambling and packet serialization deserialization The Data link layer is responsible for the creation and transmission of DLLPs data link layer packet and decoding these received p...

Page 33: ...demo software allows you to access memory and registers on the board and provides real time interaction with the CrossLink NX Bridge Board hardware to demonstrate a functional PCI Express communicati...

Page 34: ...ted an error message appears in this page Table 5 1 describes the Device Info tab Table 5 1 Device Info Tab Feature Description Lattice Device Info page Displays windows resource assigned to the devic...

Page 35: ...s on the display You can present character sequences from this page or select single characters and run them to light the display The states of the LED segments are converted to an 8 bit word value ea...

Page 36: ...tware on the CPU and the FPGA IP Table 5 3 Memory Data and Corresponding 7 Segment Display Values Memory Data 7 Segment Display Value 3F 0 06 1 5B 2 4F 3 66 4 6D 5 7D 6 07 7 7F 8 6F 9 77 A 7C B 39 C 5...

Page 37: ...selected Base Address Register BAR Data can be written to the registers by using Write button Specify the BAR offset to start writing at and the hex data in the Data field Data size should match the d...

Page 38: ...d in 32 bit mode 0xFFFFFFFF is the maximum value that can be entered Write Offset The offset where data is to be written Range of address depends on the bar size In 16 bit mode this address should be...

Page 39: ...CIe Bridge Board These IPs can be configured by clicking ipx file after opening the project in Radiant Implementation Contains the Lattice Radiant project rdf file constraints file pdc and implemented...

Page 40: ...1 SPI Flash Update If you are getting a verification error while dumping the bit file try changing the TCK frequency to a value greater than 4 The TCK Divider Setting option is in the Cable Setup dia...

Page 41: ...evice ID are valid as seen by Windows Plug n Play If the values are invalid perhaps the bitstream file is corrupt and needs to be reloaded into SPI flash If the PCIe board is shown in the list of Devi...

Page 42: ...where the file is being loaded must have Read Permission If the basic demo short cut icon is accidentally deleted then the application can be launched by double clicking on lattice_bd exe file presen...

Page 43: ...of this directory Default content is shown in Figure 7 6 Check the permissions of these file Figure 7 6 Content List of Demonstration Linux Directory The script files should have execute permission t...

Page 44: ...mers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subje...

Page 45: ...disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein ar...

Page 46: ...www latticesemi com...

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