CrossLink-NX PCIe Bridge Board Basic Demo
User Guide
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FPGA-UG-02145-1.0
4.
Demo Design Overview
4.1.
Theory of Operation
The demo runs on a standard x64 PC and accesses the CL-NX PCIe Bridge Board installed in a PCIe slot.
shows
the relationship of the hardware and software components of the demo for Lattice CL-NX PCIe Bridge board. The PCIe
IP present in the Lattice FPGA on the CL-NX PCIe Bridge Board acts as a PCIe endpoint occupying certain ranges of PCI
memory space. When the PC boots, the BIOS and OS probe the PCI Express and PCI buses and detect the devices
present on the buses and assign them ranges in the PCI memory space. The PCI memory space is mapped into the PC’s
memory space by the BIOS. Once the device driver is installed, the application software can read/write from/to the
PCIe device memory (Embedded Block RAM - EBR). The application software can also read from the PCIe configuration
space registers.
Application
User Interface or Console Based
PCIe APIs
CrossLink-NX PCIe Driver
PCIe Bus Driver
Memory Mapped I/O
User
Space
Kernel
Space
PC
CrossLink-NX
FPGA
PCIe IP Block
EBR
Byte, Short and Word Accessible
Figure 4.1. Relationship of the Hardware and Software Components
