CrossLink-NX PCIe Bridge Board Basic Demo
User Guide
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FPGA-UG-02145-1.0
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6.
Importing and Building the FPGA Demonstration
The package includes the PCIe IP, .bit file, and synthesis projects using Lattice Radiant Software for the CrossLink-NX
PCIe Bridge board.
6.1.
Hardware Directory Structure
The Hardware folder inside the package contains the following subfolders.
./CL_NX_BridgeBoard_PCIeBasicDemo
IP – Contains the pre-generated IPs used in the design for CL-NX PCIe Bridge Board. These IPs can be configured by
clicking .ipx file after opening the project in Radiant.
Implementation – Contains the Lattice Radiant project (.rdf) file, constraints file (pdc), and implemented design
and bit files.
Source – Contains RTL files required for the design.
6.2.
Building Lattice Radiant Project
To generate the bit stream file:
1.
Open the Lattice Radiant software.
2.
Click Open project and browse the LIFCL-40_PCIe_Basic_Demo.rdf file, which is located in the
BridgeBoard_PCIe_BasicDemo\Hardware\CL_NX_BridgeBoard_PCIeBasicDemo\Implementation\LIFCL-
40_PCIe_Basic_Demo folder.
3.
Once your project loads, click Task Detail View. This shows a list of actions that Lattice Radiant will perform to build
the .bit file.
4.
Select the files and reports that you want to generate.
Note: The options needed to regenerate the .bit file are selected by default.
5.
After selecting your preferred reports, click Run All.
This creates a .bit file with your project's current name in the imp1 folder.
