CrossLink LIF-MD6000 Master Link Board - Revision C
Evaluation Board User Guide
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FPGA-EB-02018-1.0
7
2.
Headers and Test Connections
shows the top view of the Master Link Rev C board. The headers and test connections on the board provide
access to LIF-MD6000 Master Link Rev C board circuits.
lists the headers and test connectors.
Table 2.1. Headers and Test Connectors
Part
Description
Setting
J1
External JTAG interface - For LCMX03 only
—
J2
mini-B USB connector
—
J3
External 12V power jack
—
J4
External clock input for MIPI D-PHY reference clock
—
J7
SW2 selector
OPEN-NOP, SHORT-CONFIGURATION RESET
J8
External 12 V terminal block
Open
J9
External 5 V terminal block
Open
J16
SPI/I
2
C programming selector for LIF-MD6000
1-2 (SPI), 2-3 (I
2
C)
J18
External SP/I
2
C access for LIF-MD6000
—
J19
SPI Flash chip select
OPEN-OFF, SHORT-ON
J22
External reference clock input for MIPI D-PHY reference clock
—
J23
LCMXO3L debug header
—
J24
VCCIO1 Bank voltage selector
1-2 (2.5 V), 2-3 (3.3 V), 2-4 (1.2 V)
J25
VCCIO2 Bank voltage selector
1-2 (2.5 V), 2-3 (3.3 V), 2-4 (1.2 V)
J26
Internal/External clock and I
2
C SDA Mux
1-2 (CLK_INT), 2-3 (CLK_EXT), 2-4 (SDA)
J27
Internal/External reference clock and I
2
C SCL Mux
1-2 (CLK_INT_REF), 2-3 (CLK_EXT_REF), 2-4 (SCL)
J28
Reveal analyzer signal connector
—
J29
Reset signal voltage selector
1-2 (VCCIO2), 2-3 (VCCIO0)
J31
External SPI/I
2
C access for LCMXO3L
—
J32
LCMXO3L configuration header
—
J35
SPI/I
2
C programming selector for LIF-MD6000
1-2 (SPI), 2-3 (I
2
C)
J36
SPI/I
2
C programming selector for LIF-MD6000
1-2 (SPI), 2-3 (I
2
C)
J37
FT2232H reset
OPEN-NORMAL OP, SHORT-RESET
SW1
External adaptor power ON/OFF
—
SW2
Configuration reset for LIF-MD6000
—
SW3
External reset for LCMXO3L
—
SW4*
External reset for LIF-MD6000
—
SW5
PMU WAKEUP Switch for LIF-MD6000
—
U7
Tx Connectors for external interface
—
U9
Tx Connectors for external interface
—
U11
Rx Connectors for external interface
—
U12
Rx Connectors for external interface
—
*Note
: Some CrossLink demos utilize this reset signal to ball G9 of Bank 2 while it is configured as a 1.2 V Bank. However, LVCMOS12
inputs are no longer supported across all 3 Banks. Lattice Diamond
®
Software 3.9 and later will not allow this signal to be placed on a
1.2 V Bank. If it is necessary to recompile one of these demo projects, the necessary modifications should be made to the project
and the board to move this reset signal to a non-1.2 V Bank on CrossLink.