CrossLink LIF-MD6000 Master Link Board - Revision C
Evaluation Board User Guide
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FPGA-EB-02018-1.0
15
7.
Breakout IO Link Board
The Breakout IO Link board connects to the CrossLink LIF-MD6000 Master Link Rev C board’s Tx or Rx connectors (U7,
U9, U11 or U12) and transfers signals to the 26-pin header (J2).
Table 7.1. Headers and Test Connectors
Part
Description
Setting
J2
13x2 Header
—
U1
Connector to interface to CrossLink Master Link Rev C board
—
Table 7.2. U1 Connector Description
Pin
Name
1
CH4_DCK_P
2
CH4_DCK_N
3
GND
4
CH4_DATA0_P
5
CH4_DATA0_N
6
GND
7
CH4_DATA1_P
8
CH4_DATA1_N
9
GND
10
SN
11
SCLK
12
GND
13
CH4_DATA2_P
14
CH4_DATA2_N
15
GND
16
CH4_DATA3_P
17
CH4_DATA3_N
18
GND
19
12V
20
12V
Pin
Name
21
TBD
22
RESETN
23
PWR_5-0V
24
GND
25
GND
26
PWR_3-3V
27
GND
28
GND
29
PWR_1-8V
30
MOSI
31
MISO
32
PWR_1-8V
33
GND
34
GND
35
PWR_3-3V
36
GND
37
GND
38
PWR_5-0V
39
SDA
40
SCL
Note
: U1 connector pin names may be different than the actual signal depending on which CrossLink LIF-MD6000 Master Link Rev C
board connector this daughter board is connected to.
