Lattice CrossLink LIF-MD6000 Master Link Board - Revision C, User Manual

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CrossLink LIF-MD6000 Master Link Board - Revision C
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal .
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02018-1.0 5
1. Introduction
This document describes the Lattice Semiconductor CrossLink™ LIF-MD6000 Master Link Board –Revision C (Rev C) that
supports a variety of demos, encompassing different signaling logic standards bridging with MIPI
®
CSI-2/DSI interface.
The board‘s key component is the CrossLink Family device that features built in MIPI D-PHY hard blocks to support
different bridging solutions.
For the latest information about this board, including optional Tx/Rx Link boards, demo files, further documentation
and more, see the Lattice website at:
www.latticesemi.com/masterlink .
For details about the CrossLink device, refer to CrossLink Family Data Sheet (FPGA-DS-02007) .
The content of this user guide includes descriptions of on-board jumper settings, programming circuit, a complete set
of schematics, and bill of materials for LIF-MD6000 Master Link Rev C board.
Refer to Appendix A, B, C, D, E, F for the schematic and BOM of the CrossLink LIF-MD6000 Master Link Rev C board and
the schematics and BOMs of the Breakout IO Link and SMA IO Link boards that are included in the demo kit.
Circuits on the development kit board:

Programming Circuit

Mini USB Type-B connector to FTDI

FTDI to CrossLink using SPI

FTDI to CrossLink using I
2
C

FTDI to XO3LF device using JTAG

CrossLink

MIPI CSI-2/DSI hard block

Bridging of multiple signaling standards

SPI flash configuration

General Purpose Input/Output

LED display

LCMXO3LF-1300E

I
2
C muxing
Figure 1.1 shows the top view of the LIF-MD6000 Master Link Rev C board and its key components. Figure 1.2 shows
the bottom view of the board.