CrossLink LIF-MD6000 Master Link Board - Revision C
Evaluation Board User Guide
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02018-1.0
27
Layout Guidelines
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Routing guidlines for MIPI & LVDS
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1)All differential routes are required to have the same length between the positive (true) and the negative (complimentary) routes.
Spacing between the positive (true) and the negative (complimentary) shall be 2 times trace width.
2)Target differential impedance shall be 100 Ohms
3)Trace length matching to be within 1.0 mm (40 mil) across the entire bus.
4)Use small humps for skew corrections
5)Place signal vias close together and remove copper in between vias.
Traces to be fully shielded with GND stitching terminating at both trace end points
6)Board trace impedance results must be within ±10 percent of target and
Power plane impedance to be /- 10 percent of target at operating frequency
MIPI &LVDS Simulation Requirement
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1)MIPI Differential Mode insertion Loss shall be > -1.6dB at 750 MHz
2)MIPI Differential Mode Return Loss shall be < -15dB at 750 MHz
3)MIPI Common Mode Return Loss shall be < -15dB at 750 MHz
4)LVDS differential mode return loss shall be < -16.5db at 600 MHz
5)LVDS common mode return loss shall be < -16.5db at 600 MHz
6)LVDS insertion loss shall be > -1.7db at 600 MHz
7)LVDS Cross coupling shall be < -22 dB for victim IO at 600MHz
8)Power plane impedance to be /- 10 percent of target at operating frequency
Date:
Size
Schematic Rev
of
Sheet
Title
Lattice Semiconductor Applications
Email: [email protected]
Board Rev
Project
28-Mar-17
B
1.0
8
8
Layout Guidelines
CrossLink_Master_Multi-Link_Board
1
Date:
Size
Schematic Rev
of
Sheet
Title
Lattice Semiconductor Applications
Email: [email protected]
Board Rev
Project
28-Mar-17
B
1.0
8
8
Layout Guidelines
CrossLink_Master_Multi-Link_Board
1
Date:
Size
Schematic Rev
of
Sheet
Title
Lattice Semiconductor Applications
Email: [email protected]
Board Rev
Project
28-Mar-17
B
1.0
8
8
Layout Guidelines
CrossLink_Master_Multi-Link_Board
1
