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Lattice CrossLink LIF-MD6000 Master Link Board - Revision C, User Manual, Page: 4 / 40

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Lattice CrossLink LIF-MD6000 Master Link Board - Revision C User Manual Download Page 4

CrossLink LIF-MD6000 Master Link Board - Revision C 

 

Evaluation Board User Guide 
 
 

© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at 

www.latticesemi.com/legal

.  

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

4 

 

FPGA-EB-02018-1.0 

Acronyms in This Document 

A list of acronyms used in this document. 

Acronym 

Definition 

CMOS 

Complementary Metal-Oxide Semiconductor 

CSI-2 

Camera Serial Interface 

DSI 

Display Serial Interface 

FTDI 

Future Technology Devices International 

I

2

C 

Inter-Integrated Circuit 

IO 

Input/Output 

LVDS 

Low-Voltage Differential Signaling 

MIPI 

Mobile Industry Processor Interface 

SPI 

Serial Peripheral Interface 

Summary of Contents for CrossLink LIF-MD6000 Master Link Board - Revision C

Page 1: ...CrossLink LIF MD6000 Master Link Board Revision C Evaluation Board User Guide FPGA EB 02018 Version 1 0 June 2018...

Page 2: ...8 1 0 Contents Acronyms in This Document 4 1 Introduction 5 2 Headers and Test Connections 7 3 Programming Circuit 8 3 1 Bridging Circuit 8 3 2 I2 C Expander 9 4 Power Supply 10 5 Status Indicators 12...

Page 3: ...Master Link Board 6 Figure 3 1 Programming Block 8 Figure 3 2 Bridging Block 9 Figure 3 3 I2 C Expander Block 9 Figure 4 1 Power Supply Block 10 Figure 6 1 Top View of SMA IO Link Board 14 Figure 6 2...

Page 4: ...pective holders The specifications and information herein are subject to change without notice 4 FPGA EB 02018 1 0 Acronyms in This Document A list of acronyms used in this document Acronym Definition...

Page 5: ...demo files further documentation and more see the Lattice website at www latticesemi com masterlink For details about the CrossLink device refer to CrossLink Family Data Sheet FPGA DS 02007 The conten...

Page 6: ...EB 02018 1 0 Tx Connectors 1 and 2 U9 U7 Power Switch SW1 External Power Input External Power Jack J3 LCMXO3L 1300E U19 USB 2 0 Mini B J2 JTAG Header J1 FTDI Chip U1 SPI Flash Device U14 Rx Connectors...

Page 7: ...eader J24 VCCIO1 Bank voltage selector 1 2 2 5 V 2 3 3 3 V 2 4 1 2 V J25 VCCIO2 Bank voltage selector 1 2 2 5 V 2 3 3 3 V 2 4 1 2 V J26 Internal External clock and I2C SDA Mux 1 2 CLK_INT 2 3 CLK_EXT...

Page 8: ...Programmer software to provide interfaces for JTAG to program MachXO3 LCMXO3LF 1300E SPI to program CrossLink and or SPI Flash Memory I2 C to program CrossLink USB Mini B J2 FTDI Chip U1 SPI Flash U1...

Page 9: ...I F CMOS D PHY Rx LVDS CMOS D PHY Rx LVDS CMOS Tx Connector 2 Tx Connector 1 D PHY I F CMOS Figure 3 2 Bridging Block 3 2 I2 C Expander Figure 3 3 shows the block diagram of the I2 C expander The LCM...

Page 10: ...ides 5 V to the various voltage regulators and is also used for device programming Each I O and core voltage rail on the board is accessible by a test point on the board The current flowing to each ra...

Page 11: ...PGA EB 02018 1 0 11 Table 4 2 Device Power Rail Summary and Test Points Voltage Rail Source Rail Current Sense Resistor Test Points 12 V 12V0 5 V 12 V 5V0 3 3 V 5 V 3V3 2 5 V 5 V 2V5 1 8 V 5 V 1 2 V 5...

Page 12: ...tion herein are subject to change without notice 12 FPGA EB 02018 1 0 5 Status Indicators The LED status indicators on the board show power configuration and application status Table 5 1 lists the sta...

Page 13: ...or DATA1_TX_P Pin 7 J6 SMA connector for DATA1_TX_N Pin 8 J7 SMA connector for DATA2_TX_P Pin 13 J8 SMA connector for DATA2_TX_N Pin 14 J9 SMA connector for DATA3_TX_P Pin 16 J10 SMA connector for DAT...

Page 14: ...patents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and informat...

Page 15: ...s signals to the 26 pin header J2 Table 7 1 Headers and Test Connectors Part Description Setting J2 13x2 Header U1 Connector to interface to CrossLink Master Link Rev C board Table 7 2 U1 Connector De...

Page 16: ...to change without notice 16 FPGA EB 02018 1 0 Table 7 3 J2 Header Description Pin Name Mapping to U1 1 3 3V N A 2 1 8V N A 3 RESETN Pin 22 4 CH4_DCK_TX_P Pin 1 5 SDA Pin 39 6 CH4_DCK_TX_N Pin 2 7 SCL...

Page 17: ...nts and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information h...

Page 18: ...s of their respective holders The specifications and information herein are subject to change without notice 18 FPGA EB 02018 1 0 8 Ordering Information Table 8 1 Ordering Information Description Orde...

Page 19: ...com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA EB 02...

Page 20: ...RX HEADER1 SPI Ext Power Adaptor 12V OnBoard LDO S Buck 1V2 1V8 2V5 3V3 5V JTAG_I F SPI I2C MIPI TX HEADER2 MIPI TX I O LVDS RX HEADER2 I2C LVDS RX In LVDS RX In SPI BANK 3 4 BANK 2 BANK 0 LCMXO3LF 1...

Page 21: ...INTERFACE CrossLink_Master_Multi Link_Board 1 R171 4 7k R7 0 L1 600ohm 500mA 1 2 R10 2k2 C194 0 1uF C5 0 1uF R14 10K C9 0 1uF R180 0 R6 0 R18 0 DNI J16 HEADER 3 1 2 3 R5 0 C16 0 1uF R9 2k2 J37 CON2 1...

Page 22: ...Email techsupport Latticesemi com Board Rev Project 28 Mar 17 B 1 0 8 3 POWER REGULATOR I F CrossLink_Master_Multi Link_Board 1 Date Size Schematic Rev of Sheet Title Lattice Semiconductor Applicatio...

Page 23: ...4 CH5_DATA0_N 5 GND 6 CH5_DATA1_P 7 CH5_DATA1_N 8 GND 9 SN 10 SCLK 11 GND 12 CH5_DATA2_P 13 CH5_DATA2_N 14 GND 15 CH5_DATA3_P 16 CH5_DATA3_N 17 GND 18 12V 19 12V 20 TBD 21 RESETN 22 PWR_5 0V 23 GND 24...

Page 24: ...J3 PB43D H3 VCCIO1 F3 VCCIO1 G4 R423 0 DNI R457 0 R425 0 R462 0 R470 0 R464 0 U11 Hirose FX12 40 Pos CH1_DCK_P 1 CH1_DCK_N 2 GND 3 CH1_DATA0_P 4 CH1_DATA0_N 5 GND 6 CH1_DATA2_P 7 CH1_DATA2_N 8 GND 9 S...

Page 25: ...uctor Applications Email techsupport Latticesemi com Board Rev Project 28 Mar 17 B 1 0 8 6 BANK0 Flash I F CrossLink_Master_Multi Link_Board 1 J27 Tri Con In1 1 Out 2 In2 3 In3 4 1K R166 KC3225A27 000...

Page 26: ...A PCLKT3_1 F11 PL5C F9 PL8B G10 PL8A G11 PL8D G8 PL8C G9 PL9B PCLKC3_0 H10 PL9A PCLKT3_0 H11 PL10D J10 PL10A J11 PL10C K11 J23 4 HEADER 1 2 3 4 R486 4 7k J32 CON3 1 2 3 C106 0 1uF D32 blue 1 2 R483 4...

Page 27: ...edance results must be within 10 percent of target and Power plane impedance to be within 10 percent of target at operating frequency MIPI LVDS Simulation Requirement 1 MIPI Differential Mode insertio...

Page 28: ...R 0402 3 C7 C20 C23 C94 C96 C10 7 C114 C141 C145 C150 C153 C188 C191 C199 C200 C202 16 10 F C0603 GRM188R61A106KE69D Murata CAP CER 10 F 10 V X5R 0603 4 C10 C11 2 18 pF C0402 C0402C180K3GACTU Kemet CA...

Page 29: ...4E357T SL44 E3 57T Vishay Semiconductor DIODE SCHOTTKY 40 V 4A DO214AB 19 D3 D10 D25 D26 D27 D28 D29 7 Green led_0603 LTST C190KGKT LITE On INC LED GREEN CLEAR 0603 SMD 20 D6 D7 D8 D9 D30 D31 D32 D33...

Page 30: ...eneral 100 Mils 2 5 header 32 J23 1 4 HEADER CON4 REGULAR 100MIL HEADER General 100 mils 4 Position header 33 J24 J25 J26 J27 4 Tri Con TriCon REGULAR 100MIL HEADER General 100 mils header 34 J28 1 CO...

Page 31: ...20FKEA Vishay RES SMD 2 2 k 1 1 10 W 0603 46 R11 R17 2 12 k R0603 RC0603FR 0712KL Yageo RES SMD 12 k 1 1 10 W 0603 47 R12 R13 R14 R123 R124 R125 R395 R399 R400 9 10 K R0603 RMCF0603JT10K0 Stackpole El...

Page 32: ...nasonic RES SMD 15 k 1 1 10 W 0402 62 R230 1 34 K R0402 ERJ 2RKF3402X Panasonic RES SMD 34 k 1 1 10 W 0402 63 R231 1 536 K R0402 ERJ 2RKF5363X Panasonic RES SMD 536 k 1 1 10 W 0402 64 R233 R436 R437 R...

Page 33: ...81 CUSTOMER SUPPLIED LIF MD6000 6MG81I Lattice Semiconductor LATTCE CROSSLNK NTERFACE MP D 78 U14 1 M25PX16 VMW6TG SOIC8 M25PX16 VMW6TG TR Micron Technology Inc IC FLASH 16 MBIT 75 MHZ 8SO 79 U15 1 AP...

Page 34: ...o o or r r A A Ap p pp p pllliiic c ca a at t tiiio o on n ns s s E E Em m ma a aiiilll t t te e ec c ch h hs s su u up p pp p po o or r rt t t L L La a at t tt t tiiic c ce e es s se e em m miii c c...

Page 35: ...turer Description 1 GND1 5 V 1 8 V 3 3 V SN SDA SCLK SCL RESETN MOSI MISO GND 12 TP_S_40_63 tp_s_40_63 DNI Square test point 40 mil inner diameter 63 mil outer diameter 2 C1 C4 2 1 F C0402 C0402C105K9...

Page 36: ...8V 3 3V 1 8V 1 8V 3 3V Date Size Schematic Rev of Sheet Title Lattice Semiconductor Applications Email techsupport Latticesemi com Board Rev Project 04 May 15 B 1 0 1 1 100MILS_DEBUG HEADER LCMXO3L 43...

Page 37: ...eference Qty Part PCB Footprint Comments Part_ Number Manufacturer Description 1 GND1 5 V 1 8 V 3 3 V SN SCLK MOSI MISO GND 9 TP_S_40_63 tp_s_40_63 DNL Square test point 40 mil inner diameter 63 mil o...

Page 38: ...marks patents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and inf...

Page 39: ......

Page 40: ...7th Floor 111 SW 5th Avenue Portland OR 97204 USA T 503 268 8000 www latticesemi com...

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