C
REATING
C
USTOM
C
OMPONENTS
IN
L
ATTICE
M
ICO
S
YSTEM
:
Custom Component Example
LatticeMico32 Hardware Developer User Guide
93
Figure 47: Verilog (.v) File
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////
//
// A simple register device with three registers:
// ----------------------------------------------
//
//////////////////////////////////////////////////////////////////////////////
module wb_reg_dev
#(
parameter CLK_MHZ = 25,
parameter reg_08_int_val = 32'h1234abcd
)
(
//---------------------------------------------------------------------
//
// WISHBONE clock/reset signals
//
//---------------------------------------------------------------------
wb_reset,//-----------------WISHBONE reset
wb_clk,//-------------------WISHBONE clock
//---------------------------------------------------------------------
//
// WISHBONE interface signals below.
// - This component does not support burst transfers.
//
//---------------------------------------------------------------------
wb_adr,//-------------------Address from master
wb_master_data,//-----------Data from master
wb_cyc,//-------------------WISHBONE cycle-valid qualifier
wb_stb,//-------------------WISHBONE transfer qualifier
wb_sel,//-------------------Data byte-lane selection
wb_we,//--------------------Write-enable
wb_slave_data,//------------Data from slave
wb_ack,//-------------------Data-valid qualifier from slave
wb_err,//-------------------Error qualifier from slave (never asserted)
wb_rty,//-------------------Retry qualifier from slave (never asserted)
//---------------------------------------------------------------------
//
// Interrupt line (active-high) that will be connected to the
// processor. Not used but for demonstrating custom component
// connectivity.
//
