ii
LatticeMico32 Hardware Developer User Guide
Copyright
Copyright © 2014 Lattice Semiconductor Corporation.
This document may not, in whole or part, be copied, photocopied, reproduced,
translated, or reduced to any electronic medium or machine-readable form without
prior written consent from Lattice Semiconductor Corporation.
Trademarks
Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation (logo), L
(stylized), L (design), Lattice (design), LSC, CleanClock, Custom Mobile Device,
DiePlus, E
2
CMOS, ECP5, Extreme Performance, FlashBAK, FlexiClock, flexiFLASH,
flexiMAC, flexiPCS, FreedomChip, GAL, GDX, Generic Array Logic, HDL Explorer,
iCE Dice, iCE40, iCE65, iCEblink, iCEcable, iCEchip, iCEcube, iCEcube2, iCEman,
iCEprog, iCEsab, iCEsocket, IPexpress, ISP, ispATE, ispClock, ispDOWNLOAD,
ispGAL, ispGDS, ispGDX, ispGDX2, ispGDXV, ispGENERATOR, ispJTAG, ispLEVER,
ispLeverCORE, ispLSI, ispMACH, ispPAC, ispTRACY, ispTURBO, ispVIRTUAL
MACHINE, ispVM, ispXP, ispXPGA, ispXPLD, Lattice Diamond, LatticeCORE,
LatticeEC, LatticeECP, LatticeECP-DSP, LatticeECP2, LatticeECP2M, LatticeECP3,
LatticeECP4, LatticeMico, LatticeMico8, LatticeMico32, LatticeSC, LatticeSCM,
LatticeXP, LatticeXP2, MACH, MachXO, MachXO2, MachXO3, MACO, mobileFPGA,
ORCA, PAC, PAC-Designer, PAL, Performance Analyst, Platform Manager,
ProcessorPM, PURESPEED, Reveal, SensorExtender, SiliconBlue, Silicon Forest,
Speedlocked, Speed Locking, SuperBIG, SuperCOOL, SuperFAST, SuperWIDE,
sysCLOCK, sysCONFIG, sysDSP, sysHSI, sysI/O, sysMEM, The Simple Machine for
Complex Design, TraceID, TransFR, UltraMOS, and specific product designations are
either registered trademarks or trademarks of Lattice Semiconductor Corporation or its
subsidiaries in the United States and/or other countries. ISP, Bringing the Best
Together, and More of the Best are service marks of Lattice Semiconductor
Corporation.
Other product names used in this publication are for identification purposes only and
may be trademarks of their respective companies.
Disclaimers
NO WARRANTIES: THE INFORMATION PROVIDED IN THIS DOCUMENT IS “AS IS”
WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY KIND INCLUDING
WARRANTIES OF ACCURACY, COMPLETENESS, MERCHANTABILITY,
NONINFRINGEMENT OF INTELLECTUAL PROPERTY, OR FITNESS FOR ANY
PARTICULAR PURPOSE. IN NO EVENT WILL LATTICE SEMICONDUCTOR
CORPORATION (LSC) OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES
WHATSOEVER (WHETHER DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
CONSEQUENTIAL, INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING
OUT OF THE USE OF OR INABILITY TO USE THE INFORMATION PROVIDED IN
THIS DOCUMENT, EVEN IF LSC HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
OR LIMITATION OF CERTAIN LIABILITY, SOME OF THE ABOVE LIMITATIONS MAY
NOT APPLY TO YOU.
LSC may make changes to these materials, specifications, or information, or to the
products described herein, at any time without notice. LSC makes no commitment to
update this documentation. LSC reserves the right to discontinue any product or
service without notice and assumes no obligation to correct any errors contained
herein or to advise any user of this document of any correction if such be made. LSC
recommends its customers obtain the latest version of the relevant information to
establish, before ordering, that the information being relied upon is current.
