C
REATING
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OMPONENTS
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ATTICE
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:
Specifying Clock/Reset and External Ports
LatticeMico32 Hardware Developer User Guide
61
Specifying Clock/Reset and External Ports
Connecting the component to the WISHBONE bus enables the LatticeMico32
microprocessor to control and access the custom component. The custom
component has its own unique input and output control signals that must be
connected outside of the platform to the rest of the system. The External Ports
tab enables these control signals to be defined so that MSB can correctly
generate a top-level Verilog module. Figure 31 shows the External Ports tab
of the Import/Create Custom Components dialog box.
This tab continues the task of building a Verilog wrapper around the custom
component. You use this tab to define the CLK_I, RST_I, and optional
INTR_O control signals. The component port specifies the signal name
presented at the <
platform
>.v top-level module created by MSB when the
platform is generated.
Figure 28: Specifying a Slave Port Connection
module MyVerilogComponent (
// wishbone interface
input [31:0] wb_slv_addr,
input [31:0] wb_slv_master_data,
input wb_slv_cyc,
input wb_slv_stb,
input [3:0] wb_slv_sel,
input wb_slv_we,
output [31:0] wb_slv_slave_data,
output wb_slv_ack,
output wb_slv_err,
output wb_slv_rty,
// mandatory clock/reset signals
input wb_clk,
input wb_rst,
// external interface (optional)
output [15:0] external_out_bus,
input [8:0] external_in_bus,
input external_in_wire,
output external_out_wire,
// interrupt signal to the processor(s)
output interrupt_signal
);
endmodule
