C
REATING
C
USTOM
C
OMPONENTS
IN
L
ATTICE
M
ICO
S
YSTEM
:
Custom Component Example
98
LatticeMico32 Hardware Developer User Guide
Functional Description
The sample custom component is a WISHBONE slave component containing
the three registers shown in Table 16 on page 99. These three registers are
general-purpose read/write registers. The lowest byte of register reg_00 is
made available as external pins of the component.
The port interface of the custom component in this example is shown
diagrammatically in Figure 50. The Verilog source code for this component is
shown in “Verilog RTL Implementation” on page 92.
Table 15 lists the input and output signals for the example component.
Figure 50: Component's Port Diagram
Table 15: Input/Output Signals in the Example Custom Component
Port Name
Direction
Width (in Bits)
Description
wb_reset
Input
1
WISHBONE reset signal
wb_clk
Input
1
WISHBONE clock signal
wb_cyc
Input
1
WISHBONE cycle qualifier signal
wb_stb
Input
1
WISHBONE strobe signal
wb_we
Input
1
WISHBONE write-enable signal
wb_adr
Input
32
WISHBONE address
wb_master_data
Input
32
WISHBONE data from master
wb_sel
Input
4
WISHBONE byte-select signal
wb_ack
Output
1
WISHBONE ack signal
wb_err
Output
1
WISHBONE error signal
