iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
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.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
34
FPGA-EB-02007-1.1
Figure A.13. Common Components
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
LATTICE SEMICONDUCTOR CORPORATION CONFIDENTIAL
PB1
CLOCK OSCILLATOR
PB2
SPARE_A1 shared with Display Controls (LED is default)
SPARE_A0 shared with Display Controls (PB is default)
SPARE_A2 shared with Display Controls (LED is default)
SPARE_D1 shared with Camera Parallel Interfaces (LED is default)
SPARE_D0 shared with Camera Parallel Interface (PB is default)
SPARE_D2 shared with Camera Parallel Interface (LED is default)
SPARE_C1 shared with Accel interrupt2 (SW is default)
SPARE_C0 shared with Accel interrupt1 (PB is default)
SPARE_C2 shared with PMOD (PB is default)
SPARE_C0 shared with PMOD (SW is default)
SPARE_C0 shared with PMOD (LED is default)
SPARE_C0 shared with PMOD (LED is default)
Common Control Headers
iCE40 UltraPlus Mobile Development Platform
FPGA_C GPIO
LED2
LED1
Common Spare Signals
VCC3V3
VCC3V3
VCCIO2_iCE_C
SPIVCCIO1_iCE_C
VCC3V3
VCCIO2_iCE_C
SPARE_A0
{2,7}
SPARE_A1
{2,7}
SPARE_A2
{2,7}
SPARE_D0
{5,10}
SPARE_D1
{5,10}
SPARE_D2
{5,10}
SPARE_C0
{4,9}
SPARE_C1
{4,9}
SPARE_C2
{4,9}
SPARE_C3
{4,9}
SPARE_C4
{4,9}
SPARE_C5
{4,9}
OSC_CLK
{2,3,4,5,8,10}
UART_RX
{2,3,4,5,6,10}
UART_TX
{2,3,4,5,6,10}
CRSTb
{2,3,4,5,6,10,11}
iCE_SS
{6,11}
M25P80_CSn
{6}
SWCLK
{6}
SWDIO
{6}
Title
Size
Document Number
Rev
Date:
Sheet
of
D
Common Components
B
13
14
Friday, November 03, 2017
Title
Size
Document Number
Rev
Date:
Sheet
of
D
Common Components
B
13
14
Friday, November 03, 2017
Title
Size
Document Number
Rev
Date:
Sheet
of
D
Common Components
B
13
14
Friday, November 03, 2017
R125
0
DNI
SW8A
SW_SPST_2
1
4
ASFLMB-27.000MHZ-LC-T
U14
GND
2
VDD
4
STDBY#
1
OUT
3
D7
Red
2
1
R128
0
R58
470
R97
10k
C135
0.1u
R130
0
R98 4.7K
R121
0
R14
10k
D2
Green
2
1
J28
Common Control
2
4
6
8
10
1
3
5
7
9
SW6
PB
R126
0
DNI
SW8B
2
3
R124
0
R79
10k
C56
0.1u
R5
0
R123
0
R122
0
R57
470
C134
0.1u
R99 4.7K
SW7
PB
R127
0
DNI
J23
Clock Source Sel
1
2
3
R129
0
R131
0
R120
0
OSC_CLK_stndby#
PB2
SW1
SW2
LED1
LED1
LED2
LED1
PB1
LED2
LED2
SW1
PB2
SW2
OSC_CLK_stndby#
