iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at
www.latticesemi.com/legal
.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02007-1.1
27
Figure A.6. Common Components- SPI
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
To jumper pool
Default: Shunt
Note position of pin#1
in reference board
SPI CONFIGURATION / FLASH
SEEED BLE MODULE
AP INTERCONNECT
LATTICE SEMICONDUCTOR CORPORATION CONFIDENTIAL
Jumper for SPI access
For programming Flash - Shunt 1,3 and 2,4 (default)
For programming iCE - Shunt 3,4 and 1,2
CRST
iCE40 UltraPlus Mobile Development Platform
DRGN5V
VCC3V3
VCC3V3
VCC3V3
VCC3V3
VSUPPLY
VSUPPLY
VSUPPLY
VSUPPLY
iCE_SO
proc_cs
{2,3,4,5,10}
iCE_SS
{11,13}
iCE_SI
iCE_SCK
{11}
proc_intr
{2,3,4,5,10}
CRSTb
{2,3,4,5,10,11,13}
flsh_miso
{11}
M25P80_CSn
{13}
flsh_mosi
{11}
UART_RX
{2,3,4,5,10,13}
CDONE
{2,3,4,5,11}
UART_TX
{2,3,4,5,10,13}
iCE_SO_B
{3}
iCE_SI_C
{4}
iCE_SI_A
{2}
iCE_SI_D
{5,10}
iCE_SI_B
{3}
iCE_SO_D
{5,10}
iCE_SO_A
{2}
iCE_SO_C
{4}
iCE_SS_B
{3}
iCE_SCK_C
{4}
iCE_SCK_A
{2}
iCE_SCK_D
{5,10}
iCE_SCK_B
{3}
iCE_SS_D
{5,10}
iCE_SS_A
{2}
iCE_SS_C
{4}
SWDIO
{13}
SWCLK
{13}
FT_RESETb
{11}
Title
Size
Document Number
Rev
Date:
Sheet
of
D
Common Components - SPI
B
6
14
Thursday, November 02, 2017
Title
Size
Document Number
Rev
Date:
Sheet
of
D
Common Components - SPI
B
6
14
Thursday, November 02, 2017
Title
Size
Document Number
Rev
Date:
Sheet
of
D
Common Components - SPI
B
6
14
Thursday, November 02, 2017
SW9B
SW_SPST_6
2
11
TP77
R4
10k
R7
10k
J18
BLE PROG SEL
1
2
3
TP88
SW9C
SW_SPST_6
3
10
R76
0
SW5B
2
3
TP78
TP89
M25P80
U37
SDI
5
SCK
6
WP
3
CS
1
SDO
2
HOLD
7
8
VCC
4
GND
TP92
TP79
R223
0
DNI
SW9D
SW_SPST_6
4
9
TP90
R77
0
C418
0.1u
TP80
R37
0
U41
DG409LDQ-T1-E3
Db
9
S4b
10
S2b
12
ENABLE
2
G
N
D
1
5
A
1
1
6
A
0
1
S4a
7
S1a
4
Da
8
S2a
5
S
3
a
6
V
+
1
4
S
1
b
1
3
S
3
b
1
1
V
-
3
R40
0
C417
0.1u
R224
0
C409
0.1u
C100
0.1u
SW9A
SW_SPST_6
1
12
TP74
TP81
J16
AP INTERCONNECT
2
4
6
8
10
1
3
5
7
9
R35
0
TP75
TP82
U42
DG409LDQ-T1-E3
Db
9
S4b
10
S2b
12
ENABLE
2
G
N
D
1
5
A
1
1
6
A
0
1
S4a
7
S1a
4
Da
8
S2a
5
S
3
a
6
V
+
1
4
S
1
b
1
3
S
3
b
1
1
V
-
3
C17
0.1u
TP83
SW9E
SW_SPST_6
5
8
R75
0
DNI
R65
10k
TP71
R67
0
DNI
SW9F
SW_SPST_6
6
7
R200
10k
R68
0
DNI
R48
0
DNI
TP84
TP72
TP76
TP91
R74 4.7K
TP85
TP73
SW4
PB
TP86
R6
10k
R45
0
DNI
J19
A3A-04PA-2SV(71)
3
4
1
2
SW5A
SW_SPST_2
1
4
TP87
U30
SeeedBLE
GND
27
SWCLK
26
SWDIO
25
VCC
24
p12
22
p13
23
p11
21
p9
19
p
8
1
8
p
7
1
7
p
6
1
6
p
5
1
5
p
4
1
4
p
3
1
3
p
2
1
2
p
1
1
1
p
0
1
0
p29
8
p28
7
p25
6
p24
5
p23
4
p17
3
p18
2
GND
1
p10
20
p30
9
R78 4.7K
iCE_SCK
iCE_SS
proc_intr
proc_cs
CRSTb
iCE_SO
iCE_SI
flsh_mosi
iCE_SCK
flsh_miso
CDONE
iCE_SI
iCE_SO
flsh_mosi
flsh_miso
CRSTb
UART_RX
UART_TX
iCE_SI
demo_sel_0
demo_sel_1
iCE_SCK
demo_sel_0
demo_sel_1
demo_sel_0
demo_sel_1
CRSTb
iCE_SS
iCE_SO
iCE_SI
iCE_SCK
MUX_EN
MUX_EN
iCE_SS
iCE_SO
