iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at
www.latticesemi.com/legal
.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
26
FPGA-EB-02007-1.1
Figure A.5. iCE40UP5K FPGA D - Camera
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
LATTICE SEMICONDUCTOR CORPORATION CONFIDENTIAL
Function Mapping from iCE40UP to Board
Note:
Place close
to DUT
iCE40 UltraPlus Mobile Development Platform
DONE_D
Note:
Place close
to DUT
Note:
Place close
to DUT
Note:
Place close
to DUT
Note:
Place close
to DUT
0 Ohm switch to support Camera
Parallel Mode
Place close to iCE40
T-type resistor switch
Note :
1) Match length within pair as well as other pairs with +/- 5% tolerence
2)Differential impedance should be 100 Ohms and 50 Ohms as a single ended signals
3)Trace match LVDSI* pins between P and N channels as well as individual pairs.
VCC Sense Resistors - 1 Ohm 0603
Add test points on both sides
SPIVCCIO1_iCE_D
SPIVCCIO1_iCE_D
VCC_iCE_D
VPP2V5_D
VCCIO2_iCE_D
VCCIO0_iCE_D
VCCPLL_IN_D
VCC_iCE_D
VCC3V3
VCC2V5
VCC1V2
VCC3V3
VCC_iCE_D
VCCPLL_IN_D
VPP2V5_D
VCCIO0_iCE_D
SPIVCCIO1_iCE_D
VCCIO2_iCE_D
VCC3V3
VCC3V3
VSUPPLY
VSUPPLY_CAM
iCE_SI_D
{6,10}
iCE_SO_D
{6,10}
iCE_SS_D
{6,10}
iCE_SCK_D
{6,10}
CDONE
{2,3,4,6,11}
CSI_HS_CLKP
{10}
CSI_HS_CLKN
{10}
CSI_HS_D0P
{10}
OSC_CLK
{2,3,4,8,10,13}
CSI_HS_D0N
{10}
SPARE_D1
{10,13}
SPARE_D2
{10,13}
SPARE_D0
{10,13}
I2C_camera_scl
{10}
I2C_camera_sda
{10}
CAM_D3
{10}
CAM_D2
{10}
UART_TX
{2,3,4,6,10,13}
UART_RX
{2,3,4,6,10,13}
proc_cs
{2,3,4,6,10}
proc_intr
{2,3,4,6,10}
CRSTb
{2,3,4,6,10,11,13}
UART_RX_D
{11}
UART_TX_D
{11}
Title
Size
Document Number
Rev
Date:
Sheet
of
D
iCE40UP5K FPGA D - Camera
B
5
14
Friday, November 03, 2017
Title
Size
Document Number
Rev
Date:
Sheet
of
D
iCE40UP5K FPGA D - Camera
B
5
14
Friday, November 03, 2017
Title
Size
Document Number
Rev
Date:
Sheet
of
D
iCE40UP5K FPGA D - Camera
B
5
14
Friday, November 03, 2017
D14
GREEN
2
1
R32
0
C120
0.1u
C133
0.1u
C118
1u
TP69
J27
iCEA Control
2
4
6
8
10
1
3
5
7
9
R100
100
R0201
DNI
R197
1
TP66
R86
100
C127
10n
TP44
R73
100
R0201
DNI
R202
1
TP68
TP46
R199
1
C83
0.1u
R91
510k
DNI
TP49
TP65
TP70
C124
10n
R157
0
Bank2
Bank1
Bank0
iCEUP5K-WLCSP30
iCE5UP5K-WLCSP30
U4
IOB_0A
E5
IOB_2A
D5
IOB_3B_G6
F5
IOB_9B
E4
IOB_10A
C3
IOB_11B_G5
F4
CRESET_B
F3
IOB_12A_G4_CDONE
D3
IOB_13B
E3
IOB_24A
B1
IOB_25B_G3
F2
IOB_32A_SPI_SO
F1
IOB_33B_SPI_SI
E1
IOB_34A_SPI_SCK
D1
IOB_35B_SPI_SS
C1
VCCPLL
B2
IOT_36B
A1
IOT_37A
A2
IOT_46B_G0
B3
IOT_47A
A4
RGB2
A5
RGB1
B5
RGB0
C5
G
N
D
B
4
G
N
D
E
2
VCC
C2
VCCIO_0
A3
SPI_VCCIO1
D2
VCCIO_2
C4
VPP_2V5
D4
C125
10u
C122
10n
R90
510k
DNI
R159
0
R22
0
C99
0.1u
R29
0
DNI
TP47
R196
1
R160
0
C119
10n
R70
2k2
C126
0.1u
TP67
R201
1
R31
0
J33
CON24A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
R158
0
R198
1
C128
1u
TP45
C123
1u
C84
1u
TP48
VCCPLL_D
iCE_SS_D
iCE_SCK_D
iCE_SI_D
iCE_SO_D
UART_TX_D
UART_RX_D
OSC_CLK_D
CDONE_D
CRSTb_D
proc_cs_D
SPARE_D0
SPARE_D1
SPARE_D2
CSI_HS_CLKP
CSI_HS_D0P
proc_intr_D
CSI_HS_D0N
CSI_HS_CLKN
I2C_camera_sda
CSI_D0_CD
CSI_D0_CD_REF
I2C_camera_scl
CDONE_D
iCE_SS_D
iCE_SCK_D
iCE_SI_D
iCE_SO_D
CDONE
CSI_HS_CLKP
CSI_HS_CLKN
CSI_HS_D0P
OSC_CLK_D
CSI_D0_CD
CSI_HS_D0N
CSI_HS_D0N
SPARE_D0
SPARE_D1
SPARE_D2
I2C_camera_scl
I2C_camera_sda
CSI_D0_CD_REF
VCCPLL_D
CSI_HS_CLKP
CSI_HS_CLKN
CSI_HS_D0P
CSI_HS_D0N
CAM_D2
CAM_D2
CSI_D0_CD_REF
CAM_D3
CAM_D3
UART_TX_D
UART_RX_D
proc_cs_D
proc_intr_D
UART_TX_D
UART_RX_D
OSC_CLK_D
proc_cs_D
SPARE_D0
SPARE_D1
SPARE_D2
iCE_SS_D
iCE_SCK_D
iCE_SI_D
iCE_SO_D
CRSTb_D
proc_intr_D
I2C_camera_sda
CSI_D0_CD_REF
I2C_camera_scl
CDONE
CDONE_D
CRSTb_D
CRSTb_D
