Lattice Semiconductor HDR-60, User Manual

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HDR-60 Base Board – Revision B
Table 5. LatticeECP3 (U2) Connections to HDMI Output (J13)
J13 Pin LatticeECP3 I/O Polarity sysIO Bank Signal Name
10 AB15 P Quad A DVI_HDOUTP0
12 AB14 N Quad A DVI_HDOUTN0
7 AB12 P Quad A DVI_HDOUTP1
9 AB13 N Quad A DVI_HDOUTN1
4 AB11 P Quad A DVI_HDOUTP2
6 AB10 N Quad A DVI_HDOUTN2
1 AB8 P Quad A DVI_HDOUTP3
3 AB9 N Quad A DVI_HDOUTN3
13 — — — CEC_OUT
15 E18 — 8 DVI_DDC_SCL
16 E17 — 8 DVI_DDC_SDA
19 A20 — 8 DVI_HPD
HiSPi Connector (J1)
The LatticeECP3 (U2) banks 1 and 2 can receive HiSPi sub-LVDS video signals from connector J1. When receiv-
ing HiSPi signals, you will need to set the LatticeECP3 input type to LVDS with differential 100 ohm termination.
The signal connections between the LatticeECP3 device and the HiSPi connector are shown in Table 6.
Table 6. LatticeECP3 (U2) Interface to HiSPi Connector J1
J1 Pin
LatticeECP3
I/O BGA Ball Polarity sysIO Bank
Differential
Signal Parallel Signal
13 K21 P 2 SLVS_0P —
11 L21 N 2 SLVS_0N —
29 L22 P 2 SLVS_1P —
27 M22 N 2 SLVS_1N —
21 P21 P 2 SLVS_2P —
19 N22 N 2 SLVS_2N —
26 M18 P 2 SLVS_3P —
24 N17 N 2 SLVS_3N —
14 L18 P 2 SLVS_4P —
12 L19 N 2 SLVS_4N HISPI_LED
22 K20 P 2 SLVS_5P —
20 K19 N 2 SLVS_5N —
17 K17 P 2 SLVS_6P —
15 K18 N 2 SLVS_6N —
25 H21 P 2 SLVS_7P —
23 H22 N 2 SLVS_7N —
18 M21 P 2 SLVS_CP —
16 M20 N 2 SLVS_CN —
10 C13 — 1 — HISPI_RESETN
28 K22 — 2 Note 1 RESERVED_1
30 J22 — 2 Note 1 HISPI_SDATA
32 C14 — 1 — HISPI_SCLK
4 A13 — 1 — VDDIO_rH
1. Routed on the HDR-60 Base Board as a differential pair.