Lattice Semiconductor HDR-60 User Manual Download Page 26

25

 HDR-60 Base Boar

d – Revision B

Figu

re

 18
. 10
0Bas

e-

T PHY/

RJ
45

5

5

4

4

3

3

2

2

1

1

D

D

C

C

B

B

A

A

1000Base-T PHY/RJ45

PHY should power down when not in use

GMII default

Place resistor near osc

n.c.

n.c.

n.c.

TRD outputs are all 100 ohm matched length diff pairs to
RJ45 connector. Place TDR(0) resistor common ends together.

+1.2v

ECP3 Symbol Pins:
* True LVDS Output
^ DQS
Density shown as -70

Place osc near U3

LED[1..4] powers up to: 1101 to set for
auto-negotiate, full duplex, 10/100/1000Base-T

LED[21] = Link speed
00: 1000Base-T (Orange & Green ON)
01: 100Base-T (Orange ON)
10: 10Base-T (Green ON)
11: no link

LED3 = Activity (Yellow ON)

All high speed signals use 50 ohm traces 

TX and RX traces are all matched length

GSRN

Ferrites are all 0.45 ohm, 200ma, 0603

RXD2

RXD0
RXD1

RXD3
RXD4
RXD5
RXD6
RXD7

RX_ER

RX_DV

RXC

TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7

TX_ER

TX_EN

TXC

CRS
COL

GTXCLK

MDC

GTXCLK

MDC

RXD5
CRS

RXD7

RXD4
COL

RXD3

RXD6

RX_ER

TXC

RXD0

MDIO

RXC

RX_DV

RXD1

TXD5

TXD4

TXD6

TX_EN
TXD0

TXD7

TXD3

TXD2
TXD1
TX_ER

P_25MHz

P_25MHz

PHY_A0

RESETN

LED4

RESETN

PHY_LOWPWR

PHY_A0
PHY_A1
PHY_A2
PHY_A3
PHY_A4

TDR0_P0
TDR0_M0

LED1
LED2

LED2
LED3

XTALVDD

PLLVDD

AVDDL

MDIO

AVDD

REGSUPPLY

REGOUT

DVDD

AVDD

BIASVDD

AVDD

XTALVDD

REGOUT

PLLVDD

REGOUT

AVDDL

REGOUT

125MHz

PHY_A1
PHY_A2
PHY_A3
PHY_A4

PHY_LOWPWR

LED1

LED3

ECP3_GSRN

125MHz

RXD2

3_3V

3_3V

3_3V

3_3V

3_3V

3_3V

3_3V

3_3V

3_3V

3_3V

3_3V

Title

Size

Project

Rev

Date:

Sheet

of

Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124

HDR-60 Base Board Schematic

B

1000Base-T PHY/RJ45

B

4

10

Wednesday, September 21, 2011

Title

Size

Project

Rev

Date:

Sheet

of

Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124

HDR-60 Base Board Schematic

B

1000Base-T PHY/RJ45

B

4

10

Wednesday, September 21, 2011

Title

Size

Project

Rev

Date:

Sheet

of

Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124

HDR-60 Base Board Schematic

B

1000Base-T PHY/RJ45

B

4

10

Wednesday, September 21, 2011

R17
100R

R0402

C31

10N

F

-0402S

M

T

R24
DNI

R0402

R30
DNI

R0603

R19
4_7K

R0603

C180

100N

F-

0603S

M

T

C201

100NF-0603SMT

R96
4_7K

R0402

R16
301K

R0402

R21
DNI

R0603

C26

10uF/

6V

3/

X

7

R

C215

100NF-0603SMT

C167

1N

F

-0402S

M

T

50 ohm ODT

100 FBGA

U3

BCM54810

NC3

A3

NC4

A4

OV

D

D

_

R

GMII

A5

OV

D

D

A6

NC21

C1

GN

D

1

C2

GN

D

2

C9

DVDD1

C1

0

DVDD2

D1

TDI

D6

TCK

D7

TMS

D8

DVDD3

D1

0

NC46

E6

NC47

E7

NC48

E8

NC49

E9

NTRST

E10

XTALI

F1

XTALO

F2

R

E

GOU

T

F3

NC56

F6

NC57

F7

NC58

F8

NC59

F9

TDO

F10

NC62

G2

REG

S

UPPL

Y

G3

NC64

G4

NC65

G5

TEST2

G8

TEST3

G9

RDAC

H1

NC72

H2

NC73

H3

NC77

H7

TEST0

H8

TEST1

H9

TRD[0]+

K1

TRD[0]-

K2

TRD[1]-

K3

TRD[1]+

K4

TRD[2]+

K5

TRD[2]-

K6

TRD[3]-

K7

TRD[3]+

K8

RX_ER

A1

RXC

A2

GTXCLK

A7

TX_EN

A8

TX_ER

A9

TXD[7]

A10

CLK125

B1

RX_DV

B2

RXD[7]

B3

RXD[6]

B4

RXD[5]

B5

TXD[2]

B6

TXD[3]

B7

TXD[4]

B8

TXD[5]

B9

TXD[6]

B10

RXD[2]

C3

RXD[3]

C4

RXD[4]

C5

TXC

C6

TXD[0]

C7

TXD[1]

C8

RG

M

II

_

SEL

[1

]

D2

RXD[1]

D3

RXD[0]

D4

COL

D5

MDC

E3

NRESET

E4

CRS

E5

MDIO

F4

LOWPWR

F5

LED[2]

G6

LED[1]

G7

LED[4]

G10

TVCOI

H4

RG

M

II

_

SEL

[0

]

H5

LED[3]

H6

PHYA[0]

H10

AVDD1

J2

AVDDL

1

J3

PHYA[2]

J9

PHYA[1]

J10

PHYA[4]

K9

PHYA[3]

K10

GN

D

3

D9

GN

D

4

E2

AVDDL

2

J4

AVDD2

J8

PL

L

V

DD

E1

XTAL

VDD

G1

BI

ASVDD

J1

GN

D

5

J5

GN

D

6

J6

GN

D

7

J7

FB20

BLM21AG601SN1D

R

J

45 (

1.

.8)

J12A

0862-1J1T-43-F

LED1_YEL_K

11

TRD3+

7

TRD3-

8

TRD4+

9

CT

6

LED1_A

12

TRD4-

10

LED2_ORN_K

15

LED2_GRN_K

13

GN

D

1

LED2_A

14

TRD2+

4

TRD2-

5

TRD1+

2

TRD1-

3

U8
LFB0001-R

TP1+

1

CT1

3

TP1-

2

NC4

4

NC5

5

MTP1-

7

NC6

6

MTP1+

8

Y4

DSC1001-CE-25.000

DSC1001-CE-25-000

DI

VCC

4

OUT

3

GND

2

EN

1

R29
DNI

R0603

C50

10uF/

6

V

3

/X

7R

C185

10uF/

6V

3/

X

7

R

C54

100NF-0603SMT

R18
1_24K

R0402

C44

100N

F-

0603S

M

T

C45

100N

F

-0603S

M

T

C187

100N

F-

0603S

M

T

C43

10uF/

6

V

3

/X

7R

C173
1uF

C0603

TP6

SW1

SW PUSHBUTTON-SPST

FB16

Z-600 ohm / 74279265

1

2

FB17

Z-600 ohm / 74279265

1

2

R98

4_7K

R0402

R23
4_7K

R0402

C184

100N

F-

0603S

M

T

C169

1N

F

-0402S

M

T

C200
1uF, X5R, 6.3V

R35

150

R0402

BANK 7

U2E

ECP3_70EA_BGA484

VCCIO7_J8

J8

VCCIO7_K7

K7

PL8A

E3

PL10A*

E5

PL8B

D4

PL10B*

E4

PL11A*

B2

PL13A^

F5

PL11B*

C2

PL13B^

F4

PL14A

D2

PL16A*

G4

PL14B

D1

PL16B*

G5

PL26A

E2

PL28A*

H4

PL26B

F3

PL28B*

J4

PL29A*

B1

PL31A^

H5

PL29B*

C1

PL31B^

H6

PL32A

G3

PL34A*/VREF1_7

E1

PL32B

G2

PL34B*/VREF2_7

F1

PL35A

G1

PL37A*/LUM0_GDLLT_IN_A

J7

PL35B

H1

PL37B*/LUM0_GDLLT_IN_B

J6

PL38A*/LUM0_GDLLT_FB_A

H2

PL40A^

J3

PL38B*/LUM0_GDLLT_FB_B

H3

PL40B^

K3

PL41A

J2

PL43A*/PCLKT7_0

K4

PL41B

J1

PL43B*/PCLKC7_0

K5

PL43E_A/LUM0_GPLLT_FB_A

K1

PL43E_C/LUM0_GPLLT_IN_A

L5

PL43E_B/LUM0_GPLLT_FB_B

L1

PL43E_D/LUM0_GPLLT_IN_B

K6

VTT7

L6

FB13

Z-600 ohm / 74279265

1

2

C181

10uF/

6

V

3

/X

7R

C114

100N

F-

0603S

M

T

RN4

4_7K

741X083472JP

1
2
3
4

8
7
6
5

C183

10uF/

6V

3/

X

7

R

R107
4_7K

R0603

TP1

TP5

C199
0.1uF

1

2

C49

10uF/

6

V

3

/X

7R

R119

4_7K

R103
4_7K

R0402

C52

33uF/

6

V

3

R20
1_24K

R0402

C112

100N

F-

0603S

M

T

FB14

Z-600 ohm / 74279265

1

2

R32

0R

R0603

C48

10uF/

6

V

3

/X

7R

R31

0R

R0603

R33

150

R0402

FB18

Z-600 ohm / 74279265

1

2

J11

BNC

1

2
3
4

FB15

Z-600 ohm / 74279265

1

2

C151

10N

F

-0402S

M

T

R115

33

R0402

R25
DNI

R0402

R34

150

R0402

C51

100N

F-

0603S

M

T

R22
DNI

R0402

TP2

FB5

Z-600 ohm / 74279265

1

2

R99

4_7K

R0402

R100 DNI

R0603

C186

100N

F

-0603S

M

T

FB3

Z-600 ohm / 74279265

1

2

C194

100N

F-

0603S

M

T

R105
4_7K

R0402

Summary of Contents for HDR-60

Page 1: ...ss mainly focus on the distribution of electronic components Line cards we deal with include Microchip ALPS ROHM Xilinx Pulse ON Everlight and Freescale Main products comprise IC Modules Potentiometer...

Page 2: ...April 2014 Revision EB70_01 2 HDR 60 Base Board Revision B User s Guide...

Page 3: ...performance features such as an enhanced DSP architecture high speed SERDES and high speed source synchronous interfaces in an economical FPGA fabric The LatticeECP3 devices also provide popular build...

Page 4: ...nnectors attached to the LatticeECP3 provide a means to investigate applications developed for High Dynamic Range image signal pro cessing The board also provides several different interconnections an...

Page 5: ...CAUTION To minimize the possibility of ESD damage the first and last electrical connections to the board should always be from test equipment chassis ground to the ground plane of the board Before co...

Page 6: ...rs then pro vide the necessary supply voltages 3 3 V 2 5 V 1 8 V 1 2 V For proper operation the 12 V DC power applied at J10 should be within the range of 11 V min to 18 V max The requirements for the...

Page 7: ...the low est jitter generation Also U4 does not use resistor divider networks to set the output voltage instead U4 is set up to directly copy its own internal 1 215 V reference voltage to its outputs...

Page 8: ...ch as J1 J2 J7 J8 and J9 which could also be considered as available prototype connectors when they are not in use Crystal Oscillators There are two crystal oscillators and two MEMS based oscillators...

Page 9: ...t type to LVDS with differential 100 ohm termination The signal connections between the LatticeECP3 device and the HiSPi connector are shown in Table 6 Table 6 LatticeECP3 U2 Interface to HiSPi Connec...

Page 10: ...9 A19 1 EXTCLK_FPGA 11 A18 1 LINE_VALID 12 B16 1 FRAME_VALID 25 B18 1 TRIGGER 27 A17 1 RESET_BAR 29 F16 1 OUTPUT_EN_BAR 31 F15 1 STANDBY 26 G15 1 SADDR 28 D15 1 SCLK 30 C15 1 SDATA 32 E15 1 OSC_ENABLE...

Page 11: ...bank 6 I Os connect to the Teradek MPEG Encoder Connector J9 The signal connections are shown in Table 10 6 C10 0 HEAD_DOUT5 7 B7 0 HEAD_DOUT6 8 A7 0 HEAD_DOUT7 9 B8 0 HEAD_DOUT8 10 A8 0 HEAD_DOUT9 13...

Page 12: ...J12 upper USB port The J12 upper USB port connects to a FTD2232D USB transceiver U5 that can produce JTAG signals able to drive the LatticeECP3 device U2 Given this the ispVM System software can detec...

Page 13: ...powered by an on board 1 8 V regulator with a 0 9 V midpoint bias termination regulator U12 The evaluation board includes terminations for address command and data signals The suggested configuration...

Page 14: ...use the PHY to evaluate a custom MAC solution During power up the resistors R21 R22 R23 R24 R25 R103 R105 and R107 set the initialized PHY configura tion to auto negotiate full duplex 10 100 1000Base...

Page 15: ...ndix A and the Broadcom BCM54810 Data Sheet for detailed information about the operation of the Ethernet PHY interface on this device Refer to Table 15 for a description of the Ethernet PHY GMII conne...

Page 16: ...t J3 as described in Appendix C Given that you might want to download to either the LatticeECP3 SRAM or the SPI Flash separate LatticeECP3 download procedures will follow that cover each type of downl...

Page 17: ...t LFE3 70EA See Figure 5 Figure 5 ispVM New Scan Configuration Setup 7 Click Edit Edit Device to edit the device A Device Information window will be opened Click the Select but ton and select the pack...

Page 18: ...Bitstream Download Operation Successful LatticeECP3 SRAM Configuration Using SPI Flash and USB Cable at J12 The LatticeECP3 SRAM can be configured easily using the ispVM System software to program the...

Page 19: ...ns select LFE3 70EA 7 Click Edit Edit Device to edit the device A Device Information window will be opened Click the Select but ton and select the package type 484 ball fpBGA then click OK 8 Click the...

Page 20: ...the bitstream download progress indictor will pop up as shown in Figure 13 When using the built in USB down load cable it will take about two minutes to erase program and verify the bitstream loaded p...

Page 21: ...CP3 U2 from the external SPI Flash U9 in two seconds and the DONE LED LED3 will light up References HDR 60 Video Camera Development Kit web page DS1021 LatticeECP3 Family Data Sheet HB1009 LatticeECP3...

Page 22: ...3 70EAHDR60 EVN 21 HDR 60 Base Board Revision B Ordering Information Technical Support Assistance e mail techsupport latticesemi com Internet www latticesemi com Revision History Date Version Change S...

Page 23: ...Bit Sheet 9 Teradek MPEG Encoder USB Sheet 8 Nanovesta Head Board Sheet 4 Nanovesta Head Board Title Size Project Rev Date Sheet of Lattice Semiconductor Corporation 5555 N E Moore Court Hillsboro Or...

Page 24: ...sboro Oregon 97124 HDR 60 Base Board Schematic B Voltage Regulators B 2 10 Wednesday September 21 2011 R51 22_1K 0603SMT R50 51k C68 PP7 1 2 C8 22uF 6 3V R44 51k C81 C85 22uF 6 3V PP4 1 2 C74 C207 22p...

Page 25: ...56 T12 57 P2 58 E21 59 C11 60 AA12 61 Y16 62 V14 63 AA16 64 H18 65 M12 66 R5 67 W16 68 AB22 69 H8 70 N10 71 E14 72 U10 73 F2 98 N11 97 K13 96 B9 95 G12 94 V2 93 K8 92 M16 91 Y4 90 N12 89 AA7 88 U13 8...

Page 26: ...F7 NC58 F8 NC59 F9 TDO F10 NC62 G2 REGSUPPLY G3 NC64 G4 NC65 G5 TEST2 G8 TEST3 G9 RDAC H1 NC72 H2 NC73 H3 NC77 H7 TEST0 H8 TEST1 H9 TRD 0 K1 TRD 0 K2 TRD 1 K3 TRD 1 K4 TRD 2 K5 TRD 2 K6 TRD 3 K7 TRD 3...

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