3
HDR-60 Base Board – Revision B
• Built-in USB 2.0 download to LatticeECP3
• Can be configured for a flywire ispDOWNLOAD™ cable connection
• HiSPi and parallel video data path connections with selectable VCCIO (1.8 V/2.5 V/3.3 V)
• Connectors for Aptina standard Head Board with USB 2.0 interface
• Connector for Teradek Capella H.264 codec board
• Test point connections to 19 I/O pins for prototyping
• Two MEMS and two crystal oscillators
• HDMI/DVI output using four channels (one quad) of differential SERDES
• 5.0 V, 3.3 V, 2.5 V, 1.8 V, 1.2 V voltages are generated from a single 12 V power source
• ispVM™ System programming support
General Description
The heart of the HDR-60 Base Board is the LatticeECP3 FPGA. The devices and connectors attached to the
LatticeECP3 provide a means to investigate applications developed for High Dynamic Range image signal pro-
cessing. The board also provides several different interconnections and support devices that permit it to be used
for a variety of purposes. The HiSPi and parallel video input, DDR2 memory, Tri-speed Ethernet PHY, and HDMI
output are useful for applications using Lattice IP cores. A modest number of test points were added around the
board for general purpose LatticeECP3 I/O usage. The SPI memory showcases the fail-safe capabilities of the
LatticeECP3. Figure 1 is the block diagram for the HDR-60 Video Camera Development Kit.
Figure 1. HDR-60 Video Camera Development Kit Block Diagram
Refclk
Q
u
ad
A
Bank 6
Bank 7
Bank 0
Bank 1
Bank 2
Bank 3
SERDES
Ch3
Ch2
Ch1
Ch0
Teradek MPEG
Ethernet
Aptina
Head Board
N
ano
V
esta
Head Board
LatticeECP3
-70EA
4
8
4 fpBGA
HDMI
DDR2 SDRAM
27 MHz
25MHz
