![Lattice Semiconductor HDR-60 User Manual Download Page 8](http://html1.mh-extra.com/html/lattice-semiconductor/hdr-60/hdr-60_user-manual_3831166008.webp)
7
HDR-60 Base Board – Revision B
Default Jumper Settings
Figure 3. Default Jumpers
LatticeECP3
Aptina Head Board
Cypress Device
SCL
SDA
On: 1.8V
J4
J5
J6
Off: 2.5V
On: 3.3V
VDDIO
Figure 3 shows the HDR-60 Base Board default jumpers settings for VDDIO set to 2.5 V. By installing a jumper on
J4 in the upper position, the VDDIO will change to 1.8 V and on the lower position, the VDDIO will change to 3.3 V.
Only when using the Aptina Head Board, do the serial clock and data signals, J5 and J6 need to be of concern. J5
and J6 select whether the Aptina Head Board will be sourced from the Cypress device (U6) directly or from the
LatticeECP3. Moving the jumpers from the lower position on J5 and J6 to the upper position will change the source
of the serial clock and data to be from the LatticeECP3 device (U2).
Prototype Areas
For general purpose I/O testing or monitoring, 19 unconnected test points with reference labels TP1, 2, … are pro-
vided for direct access to the LatticeECP3 device. Other I/Os on the LatticeECP3 are brought to dedicated connec-
tors such as J1, J2, J7, J8 and J9, which could also be considered as available prototype connectors when they are
not in use.
Crystal Oscillators
There are two crystal oscillators and two MEMS-based oscillators on the HDR-60 Base Board. The two crystals are
used for the two USB port connections. One MEMS-based oscillator is used to set the reference frequency for the
Ethernet PHY, while the other is used to drive inputs to the LatticeECP3 (U2). Table 4 shows the oscillator usage.
Locations Y1 and Y4 are the MEMS-based oscillators.
Table 4. Crystal Oscillators Used on the HDR-60 Base Board
Location
Frequency
Comment
LatticeECP3 Input
I/O Setting
Y1
27.000 MHz
DDR2 U2 pin R17
MPEG U2 pin T3
SSTL18 (no term)
LVCMOS33
Y2
6.000 MHz
USB FTD2232D U5 pin 43
(upper USB port at J12)
—
Y3
24.000 MHz
USB Cypress U6 pin 11
(lower USB port at J12)
—
Y4
25.000 MHz
Ethernet PHY U3 pin F1
—
DVI Video Output
The LatticeECP3 (U2) SERDES Quad A outputs drive the HDMI connector (J13) through inline AC coupling capac-
itors C55, C56, C57, C58, C218, C219, C220, and C221. The SERDES signal paths are 50 ohms between the
LatticeECP3 outputs to the HDMI connector on the HDR-60 Base Board. The DVI signal connections between the
LatticeECP3 device and the HDMI connector are shown in Table 5.