Lattice Semiconductor HDR-60 User Manual Download Page 8

7

 HDR-60 Base Board – Revision B

Default Jumper Settings

Figure 3. Default Jumpers

LatticeECP3

Aptina Head Board

Cypress Device

SCL

SDA

On: 1.8V

J4

J5

J6

Off: 2.5V

On: 3.3V

VDDIO

Figure 3 shows the HDR-60 Base Board default jumpers settings for VDDIO set to 2.5 V. By installing a jumper on 
J4 in the upper position, the VDDIO will change to 1.8 V and on the lower position, the VDDIO will change to 3.3 V. 

Only when using the Aptina Head Board, do the serial clock and data signals, J5 and J6 need to be of concern. J5 
and J6 select whether the Aptina Head Board will be sourced from the Cypress device (U6) directly or from the 
LatticeECP3. Moving the jumpers from the lower position on J5 and J6 to the upper position will change the source 
of the serial clock and data to be from the LatticeECP3 device (U2).

Prototype Areas

For general purpose I/O testing or monitoring, 19 unconnected test points with reference labels TP1, 2, … are pro-
vided for direct access to the LatticeECP3 device. Other I/Os on the LatticeECP3 are brought to dedicated connec-
tors such as J1, J2, J7, J8 and J9, which could also be considered as available prototype connectors when they are 
not in use.

Crystal Oscillators

There are two crystal oscillators and two MEMS-based oscillators on the HDR-60 Base Board. The two crystals are 
used for the two USB port connections. One MEMS-based oscillator is used to set the reference frequency for the 
Ethernet PHY, while the other is used to drive inputs to the LatticeECP3 (U2). Table 4 shows the oscillator usage. 
Locations Y1 and Y4 are the MEMS-based oscillators.

Table 4. Crystal Oscillators Used on the HDR-60 Base Board

Location

Frequency

Comment

LatticeECP3 Input 

I/O Setting

Y1

27.000 MHz

DDR2 U2 pin R17
MPEG U2 pin T3

SSTL18 (no term)

LVCMOS33

Y2

6.000 MHz

USB FTD2232D U5 pin 43
(upper USB port at J12)

Y3

24.000 MHz

USB Cypress U6 pin 11
(lower USB port at J12)

Y4

25.000 MHz

Ethernet PHY U3 pin F1

DVI Video Output

The LatticeECP3 (U2) SERDES Quad A outputs drive the HDMI connector (J13) through inline AC coupling capac-
itors C55, C56, C57, C58, C218, C219, C220, and C221. The SERDES signal paths are 50 ohms between the 
LatticeECP3 outputs to the HDMI connector on the HDR-60 Base Board. The DVI signal connections between the 
LatticeECP3 device and the HDMI connector are shown in Table 5.

Summary of Contents for HDR-60

Page 1: ...ss mainly focus on the distribution of electronic components Line cards we deal with include Microchip ALPS ROHM Xilinx Pulse ON Everlight and Freescale Main products comprise IC Modules Potentiometer...

Page 2: ...April 2014 Revision EB70_01 2 HDR 60 Base Board Revision B User s Guide...

Page 3: ...performance features such as an enhanced DSP architecture high speed SERDES and high speed source synchronous interfaces in an economical FPGA fabric The LatticeECP3 devices also provide popular build...

Page 4: ...nnectors attached to the LatticeECP3 provide a means to investigate applications developed for High Dynamic Range image signal pro cessing The board also provides several different interconnections an...

Page 5: ...CAUTION To minimize the possibility of ESD damage the first and last electrical connections to the board should always be from test equipment chassis ground to the ground plane of the board Before co...

Page 6: ...rs then pro vide the necessary supply voltages 3 3 V 2 5 V 1 8 V 1 2 V For proper operation the 12 V DC power applied at J10 should be within the range of 11 V min to 18 V max The requirements for the...

Page 7: ...the low est jitter generation Also U4 does not use resistor divider networks to set the output voltage instead U4 is set up to directly copy its own internal 1 215 V reference voltage to its outputs...

Page 8: ...ch as J1 J2 J7 J8 and J9 which could also be considered as available prototype connectors when they are not in use Crystal Oscillators There are two crystal oscillators and two MEMS based oscillators...

Page 9: ...t type to LVDS with differential 100 ohm termination The signal connections between the LatticeECP3 device and the HiSPi connector are shown in Table 6 Table 6 LatticeECP3 U2 Interface to HiSPi Connec...

Page 10: ...9 A19 1 EXTCLK_FPGA 11 A18 1 LINE_VALID 12 B16 1 FRAME_VALID 25 B18 1 TRIGGER 27 A17 1 RESET_BAR 29 F16 1 OUTPUT_EN_BAR 31 F15 1 STANDBY 26 G15 1 SADDR 28 D15 1 SCLK 30 C15 1 SDATA 32 E15 1 OSC_ENABLE...

Page 11: ...bank 6 I Os connect to the Teradek MPEG Encoder Connector J9 The signal connections are shown in Table 10 6 C10 0 HEAD_DOUT5 7 B7 0 HEAD_DOUT6 8 A7 0 HEAD_DOUT7 9 B8 0 HEAD_DOUT8 10 A8 0 HEAD_DOUT9 13...

Page 12: ...J12 upper USB port The J12 upper USB port connects to a FTD2232D USB transceiver U5 that can produce JTAG signals able to drive the LatticeECP3 device U2 Given this the ispVM System software can detec...

Page 13: ...powered by an on board 1 8 V regulator with a 0 9 V midpoint bias termination regulator U12 The evaluation board includes terminations for address command and data signals The suggested configuration...

Page 14: ...use the PHY to evaluate a custom MAC solution During power up the resistors R21 R22 R23 R24 R25 R103 R105 and R107 set the initialized PHY configura tion to auto negotiate full duplex 10 100 1000Base...

Page 15: ...ndix A and the Broadcom BCM54810 Data Sheet for detailed information about the operation of the Ethernet PHY interface on this device Refer to Table 15 for a description of the Ethernet PHY GMII conne...

Page 16: ...t J3 as described in Appendix C Given that you might want to download to either the LatticeECP3 SRAM or the SPI Flash separate LatticeECP3 download procedures will follow that cover each type of downl...

Page 17: ...t LFE3 70EA See Figure 5 Figure 5 ispVM New Scan Configuration Setup 7 Click Edit Edit Device to edit the device A Device Information window will be opened Click the Select but ton and select the pack...

Page 18: ...Bitstream Download Operation Successful LatticeECP3 SRAM Configuration Using SPI Flash and USB Cable at J12 The LatticeECP3 SRAM can be configured easily using the ispVM System software to program the...

Page 19: ...ns select LFE3 70EA 7 Click Edit Edit Device to edit the device A Device Information window will be opened Click the Select but ton and select the package type 484 ball fpBGA then click OK 8 Click the...

Page 20: ...the bitstream download progress indictor will pop up as shown in Figure 13 When using the built in USB down load cable it will take about two minutes to erase program and verify the bitstream loaded p...

Page 21: ...CP3 U2 from the external SPI Flash U9 in two seconds and the DONE LED LED3 will light up References HDR 60 Video Camera Development Kit web page DS1021 LatticeECP3 Family Data Sheet HB1009 LatticeECP3...

Page 22: ...3 70EAHDR60 EVN 21 HDR 60 Base Board Revision B Ordering Information Technical Support Assistance e mail techsupport latticesemi com Internet www latticesemi com Revision History Date Version Change S...

Page 23: ...Bit Sheet 9 Teradek MPEG Encoder USB Sheet 8 Nanovesta Head Board Sheet 4 Nanovesta Head Board Title Size Project Rev Date Sheet of Lattice Semiconductor Corporation 5555 N E Moore Court Hillsboro Or...

Page 24: ...sboro Oregon 97124 HDR 60 Base Board Schematic B Voltage Regulators B 2 10 Wednesday September 21 2011 R51 22_1K 0603SMT R50 51k C68 PP7 1 2 C8 22uF 6 3V R44 51k C81 C85 22uF 6 3V PP4 1 2 C74 C207 22p...

Page 25: ...56 T12 57 P2 58 E21 59 C11 60 AA12 61 Y16 62 V14 63 AA16 64 H18 65 M12 66 R5 67 W16 68 AB22 69 H8 70 N10 71 E14 72 U10 73 F2 98 N11 97 K13 96 B9 95 G12 94 V2 93 K8 92 M16 91 Y4 90 N12 89 AA7 88 U13 8...

Page 26: ...F7 NC58 F8 NC59 F9 TDO F10 NC62 G2 REGSUPPLY G3 NC64 G4 NC65 G5 TEST2 G8 TEST3 G9 RDAC H1 NC72 H2 NC73 H3 NC77 H7 TEST0 H8 TEST1 H9 TRD 0 K1 TRD 0 K2 TRD 1 K3 TRD 1 K4 TRD 2 K5 TRD 2 K6 TRD 3 K7 TRD 3...

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