Lattice Semiconductor HDR-60 User Manual Download Page 25

24

 HDR-60 Base Boar

d – Revision B

Figu

re

 17
. Core

 P

o

we
r

5

5

4

4

3

3

2

2

1

1

D

D

C

C

B

B

A

A

Core Power

28 mA max

100 mA max

302 mA max

0.46 v drop at 500 mA max

25V

6.3V
0805

0805

2.3v minimum input voltage

+1.2 v
500 mA

ECP3 Symbol Pins:
* True LVDS Output
^ DQS
Density shown as -70

25V

0805

+1.2 v
500 mA

VCCPLL

PCSA_VCCIB

PCSA_VCCOB

VCCA

3_3v

VCCA

3_3V

VCC_CORE

3_3V

1_2v

3_3v

Title

Size

Project

Rev

Date:

Sheet

of

Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124

HDR-60 Base Board Schematic

B

Core Power

B

3

10

Wednesday, September 21, 2011

Title

Size

Project

Rev

Date:

Sheet

of

Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124

HDR-60 Base Board Schematic

B

Core Power

B

3

10

Wednesday, September 21, 2011

Title

Size

Project

Rev

Date:

Sheet

of

Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124

HDR-60 Base Board Schematic

B

Core Power

B

3

10

Wednesday, September 21, 2011

C25

1U

F-

16V

-0805S

M

T

C145

10N

F

-0402S

M

T

10uF

COUT2

FB2

BLM41PG600SN1

C155

1N

F-

0402S

M

T

C170

100N

F

-0402S

M

T

C137

100N

F-

0402S

M

T

+

C113

22U

F

-16V

-T

A

N

TB

S

M

T

GND

GND

GND

GND

U2L

ECP3_70EA_BGA484

1

R13

2

L11

3

M10

4

E8

5

U17

6

U14

7

N13

8

AB16

9

N21

10

G11

11

K10

12

C19

13

T13

14

K11

15

P18

16

AA11

17

V7

18

M3

19

L10

20

V9

21

H15

22

F6

23

L13

24

F17

25

T11

26

R8

27

B1

7

28

A1

29

R1

5

30

AA1

4

31

V8

32

P1

6

33

U6

34

N8

35

U2

1

36

J21

37

K1

5

38

L20

39

H1

3

40

L16

41

A2

2

42

J5

43

V1

6

44

W7

45

AA8

46

B1

3

47

B5

48

AB7

49

L7

50

H10

51

M11

52

W20

53

M7

54

V15

55

AA9

56

T12

57

P2

58

E21

59

C11

60

AA12

61

Y16

62

V14

63

AA16

64

H18

65

M12

66

R5

67

W16

68

AB22

69

H8

70

N10

71

E14

72

U10

73

F2

98

N1

1

97

K1

3

96

B9

95

G1

2

94

V2

93

K8

92

M1

6

91

Y4

90

N1

2

89

AA7

88

U1

3

87

AA1

0

86

AA1

5

85

D3

84

M1

3

83

AB1

82

AA1

3

81

T10

80

U9

79

L12

78

AA1

8

77

K1

2

76

R1

0

75

K2

74

Y7

XRES

N15

PP6

1

2

C129

10N

F-

0402S

M

T

C148

10N

F-

0402S

M

T

C156

100N

F-

0402S

M

T

C136

10N

F-

0402S

M

T

PP5

1

2

FB10

BLM41PG600SN1

CBYP2

0.01uF

C149

10N

F-

0402S

M

T

U2M

ECP3_70EA_BGA484

VCCPLL_L_K9

K9

VCCPLL_L_N9

N9

VCCPLL_R_K14

K14

VCCPLL_R_N14

N14

TP26

C128

100N

F

-0

402S

M

T

C144

100N

F

-0402S

M

T

C146

100N

F-

0402S

M

T

C126

1N

F-

0402S

M

T

FB1

BLM41PG600SN1

C142

1N

F-

0402S

M

T

R90
10k1%

C168

1U

F-

16V

-0805S

M

T

C165

100N

F-

0402S

M

T

C46

1U

F-

16V

-0

805S

M

T

C139

10N

F-

0402S

M

T

CBYP1

0.01uF

+

C154

22U

F-

16V-

TAN

T

BSM

T

+

C182

22U

F

-16V

-T

A

N

TB

S

M

T

1uF

CIN2

VCC

U2J

ECP3_70EA_BGA484

1

J11

2

J9

3

P11

4

P12

5

J14

6

J13

7

M14

8

M9

9

P9

10

L9

11

P14

12

P10

13

J12

14

J10

15

L14

16

P13

C163

10N

F-

0402S

M

T

C147

10N

F

-0402S

M

T

C162

10N

F-

0402S

M

T

TP25

TP24

C134

10N

F

-0402S

M

T

C42

1U

F-

16V

-0805S

M

T

C160

1N

F-

0402S

M

T

FB4

BLM41PG600SN1

C131

1N

F-

0402S

M

T

TP23

C143

10N

F-

0402S

M

T

C161

1N

F-

0402S

M

T

+

C179

2

2

UF-

1

6

V

-T

ANTBSM

T

10uF

COUT1

U4

LT3029EDE

BYP1

1

VI

N1

_

1

3

13

BYP2

8

ADJ2

9

GN

D

5

ADJ1

16

EN

15

VOUT1

4

EN2

10

VOUT2

7

VI

N2

12

VOUT1_3

3

VOUT2_6

6

VI

N1

14

VI

N2

_

1

1

11

NC

2

GN

D

_

P

A

D

17

C152

100N

F-

0402S

M

T

C177

100N

F-

0402S

M

T

C158

10N

F

-0402S

M

T

C153

1N

F-

0402S

M

T

C133

10N

F-

0402S

M

T

C41

1U

F-

16V

-0

805S

M

T

C159

100N

F-

0402S

M

T

C141

10N

F-

0402S

M

T

C47

100N

F-

0402S

M

T

U2K

ECP3_70EA_BGA484

VCCAUX_M8

M8

VCCAUX_R11

R11

VCCAUX_H11

H11

VCCAUX_M15

M15

VCCAUX_R12

R12

VCCAUX_H12

H12

VCCAUX_L8

L8

VCCAUX_L15

L15

VCCA_V10

V10

VCCA_V13

V13

VCCA_U12

U12

VCCA_U11

U11

+

C178

2

2

U

F-

1

6

V-

TANTBSM

T

1uF

CIN1

Summary of Contents for HDR-60

Page 1: ...ss mainly focus on the distribution of electronic components Line cards we deal with include Microchip ALPS ROHM Xilinx Pulse ON Everlight and Freescale Main products comprise IC Modules Potentiometer...

Page 2: ...April 2014 Revision EB70_01 2 HDR 60 Base Board Revision B User s Guide...

Page 3: ...performance features such as an enhanced DSP architecture high speed SERDES and high speed source synchronous interfaces in an economical FPGA fabric The LatticeECP3 devices also provide popular build...

Page 4: ...nnectors attached to the LatticeECP3 provide a means to investigate applications developed for High Dynamic Range image signal pro cessing The board also provides several different interconnections an...

Page 5: ...CAUTION To minimize the possibility of ESD damage the first and last electrical connections to the board should always be from test equipment chassis ground to the ground plane of the board Before co...

Page 6: ...rs then pro vide the necessary supply voltages 3 3 V 2 5 V 1 8 V 1 2 V For proper operation the 12 V DC power applied at J10 should be within the range of 11 V min to 18 V max The requirements for the...

Page 7: ...the low est jitter generation Also U4 does not use resistor divider networks to set the output voltage instead U4 is set up to directly copy its own internal 1 215 V reference voltage to its outputs...

Page 8: ...ch as J1 J2 J7 J8 and J9 which could also be considered as available prototype connectors when they are not in use Crystal Oscillators There are two crystal oscillators and two MEMS based oscillators...

Page 9: ...t type to LVDS with differential 100 ohm termination The signal connections between the LatticeECP3 device and the HiSPi connector are shown in Table 6 Table 6 LatticeECP3 U2 Interface to HiSPi Connec...

Page 10: ...9 A19 1 EXTCLK_FPGA 11 A18 1 LINE_VALID 12 B16 1 FRAME_VALID 25 B18 1 TRIGGER 27 A17 1 RESET_BAR 29 F16 1 OUTPUT_EN_BAR 31 F15 1 STANDBY 26 G15 1 SADDR 28 D15 1 SCLK 30 C15 1 SDATA 32 E15 1 OSC_ENABLE...

Page 11: ...bank 6 I Os connect to the Teradek MPEG Encoder Connector J9 The signal connections are shown in Table 10 6 C10 0 HEAD_DOUT5 7 B7 0 HEAD_DOUT6 8 A7 0 HEAD_DOUT7 9 B8 0 HEAD_DOUT8 10 A8 0 HEAD_DOUT9 13...

Page 12: ...J12 upper USB port The J12 upper USB port connects to a FTD2232D USB transceiver U5 that can produce JTAG signals able to drive the LatticeECP3 device U2 Given this the ispVM System software can detec...

Page 13: ...powered by an on board 1 8 V regulator with a 0 9 V midpoint bias termination regulator U12 The evaluation board includes terminations for address command and data signals The suggested configuration...

Page 14: ...use the PHY to evaluate a custom MAC solution During power up the resistors R21 R22 R23 R24 R25 R103 R105 and R107 set the initialized PHY configura tion to auto negotiate full duplex 10 100 1000Base...

Page 15: ...ndix A and the Broadcom BCM54810 Data Sheet for detailed information about the operation of the Ethernet PHY interface on this device Refer to Table 15 for a description of the Ethernet PHY GMII conne...

Page 16: ...t J3 as described in Appendix C Given that you might want to download to either the LatticeECP3 SRAM or the SPI Flash separate LatticeECP3 download procedures will follow that cover each type of downl...

Page 17: ...t LFE3 70EA See Figure 5 Figure 5 ispVM New Scan Configuration Setup 7 Click Edit Edit Device to edit the device A Device Information window will be opened Click the Select but ton and select the pack...

Page 18: ...Bitstream Download Operation Successful LatticeECP3 SRAM Configuration Using SPI Flash and USB Cable at J12 The LatticeECP3 SRAM can be configured easily using the ispVM System software to program the...

Page 19: ...ns select LFE3 70EA 7 Click Edit Edit Device to edit the device A Device Information window will be opened Click the Select but ton and select the package type 484 ball fpBGA then click OK 8 Click the...

Page 20: ...the bitstream download progress indictor will pop up as shown in Figure 13 When using the built in USB down load cable it will take about two minutes to erase program and verify the bitstream loaded p...

Page 21: ...CP3 U2 from the external SPI Flash U9 in two seconds and the DONE LED LED3 will light up References HDR 60 Video Camera Development Kit web page DS1021 LatticeECP3 Family Data Sheet HB1009 LatticeECP3...

Page 22: ...3 70EAHDR60 EVN 21 HDR 60 Base Board Revision B Ordering Information Technical Support Assistance e mail techsupport latticesemi com Internet www latticesemi com Revision History Date Version Change S...

Page 23: ...Bit Sheet 9 Teradek MPEG Encoder USB Sheet 8 Nanovesta Head Board Sheet 4 Nanovesta Head Board Title Size Project Rev Date Sheet of Lattice Semiconductor Corporation 5555 N E Moore Court Hillsboro Or...

Page 24: ...sboro Oregon 97124 HDR 60 Base Board Schematic B Voltage Regulators B 2 10 Wednesday September 21 2011 R51 22_1K 0603SMT R50 51k C68 PP7 1 2 C8 22uF 6 3V R44 51k C81 C85 22uF 6 3V PP4 1 2 C74 C207 22p...

Page 25: ...56 T12 57 P2 58 E21 59 C11 60 AA12 61 Y16 62 V14 63 AA16 64 H18 65 M12 66 R5 67 W16 68 AB22 69 H8 70 N10 71 E14 72 U10 73 F2 98 N11 97 K13 96 B9 95 G12 94 V2 93 K8 92 M16 91 Y4 90 N12 89 AA7 88 U13 8...

Page 26: ...F7 NC58 F8 NC59 F9 TDO F10 NC62 G2 REGSUPPLY G3 NC64 G4 NC65 G5 TEST2 G8 TEST3 G9 RDAC H1 NC72 H2 NC73 H3 NC77 H7 TEST0 H8 TEST1 H9 TRD 0 K1 TRD 0 K2 TRD 1 K3 TRD 1 K4 TRD 2 K5 TRD 2 K6 TRD 3 K7 TRD 3...

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