4: Open-QTM 410 Carrier Board
Open-Q 410 Dev Kit User Guide
23
The table below describes the pin out for each connector. Signal directions listed are relative to the carrier
board. Unless noted otherwise, single ended signals are referenced to +1.8V.
NOTE:
The MIPI CSI0 connector (J701) has a 4-lane MIPI interface, while the MIPI CSI1 connector (J702) is only has
a 2-lane MIPI interface.
Table 4 – MIPI CSI Camera Connector Pinout (For Rev 0100)
Pin#
Signal Name (J701)
Signal Name (J702)
Description
1, 7, 13,
19, 25,
31, 4, 8,
12, 16,
24, 32,
38
GND
GND
Ground
3, 5
CSI0_CLK_N / P
CSI1_CLK_N
Input. MIPI CSI0 / CSI1 clock lane
9, 11
CSI0_LANE0_N / P
CSI1_LANE0_N / P
Input. MIPI CSI0 / CSI1 data lane 0
15, 17
CSI0_LANE1_N / P
CSI1_LANE1_N / P
Input. MIPI CSI0 / CSI1 data lane 1
21, 23
CSI0_LANE2_N / P
NC
Input. MIPI CSI0 data lane 2
27, 29
CSI0_LANE3_N / P
NC
Input. MIPI CSI0 data lane 3
33
CSI0_MCLK (APQ8016E
GPIO26)
CSI1_MCLK (APQ8016E
GPIO27)
Output. Camera master clock.
35
CSI0_RST (APQ8016E
GPIO35)
CSI1_RST (APQ8016E
GPIO28)
Output. Camera reset.
37, 39,
40
VPH_PWR_3P7
VPH_PWR_3P7
Power output. +3.7V.
2
VREG_L10_2P8
VREG_L10_2P8
Power output. Connected to PM8916
VREG_L10 LDO output. Default is +2.8V
6
VREG_L6_1P8
VREG_L6_1P8
Power output. Connected to PM8916
VREG_L6 LDO output. Default is +1.8V
10
VREG_L17_2P85
VREG_L17_2P85
Power output. Connected to PM8916
VREG_L17 LDO output. Default is +2.85V
18
CSI0_PWDN (APQ8016E
GPIO34)
CSI0_PWDN (APQ8016E
GPIO33)
Output. Camera power down.
20, 22
CCI0_I2C_SCL / SDA
CCI0_I2C_SCL / SDA
Camera CCI0 I2C clock interface
34, 36
BLSP6_0 / 1
BLSP6_0 / 1
Spare I2C port.
14, 26,
28, 30
NC
NC
Not connected.
