Laird BL600-SA, Hardware Integration Manual

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BL600-Sx Hardware Integration Guide
Single Mode BLE Module
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2 CONN-HIG-BL600
R
EVISION
H
ISTORY
Version Revision Date Change History
1.0 16 April13 Initial Release
1.1 5 July13
Added:
To
Table 1 , smart BASIC runtime engine FW upgrade via UART.
To Table 1 , smart BASIC application download via OTA.
Section 3.3.4 OTA (Over the Air) smart BASIC application download
Updated:
Table 1 , make it clear number of SPI (x1), I2C(x1) interfaces and ADC channels.
Table 2 (pin list), footnote mentions SIO_7 has Internal Pull down (default in
FW).
Section 5.2 (clocks) , corrected 32.768 crystal accuracy to +/-20ppm. Added
16MHz crystal accuracy (+/-10ppm).
Section 6.1 Circuit – circuit HW integration suggestion), on SIO_7 pin and Over
the Air smart BASIC application download feature.
Figure 13: BL600 Mechanical drawings – BL600 Mechanical drawing to add
measurements of the half-moon shaped positioning holes.
1.2 25 Oct 2013
Updated Recommended Operating Parameters notes to reflect 2.7 ms rather
than 2.7 µs.
1.3 12 Dec 2013 Added baking schedule information.
1.4 20 Dec 2013
Added:
ADC (AIN) input impedance into
Table 6 , Section 0 .
AIN (ADC) impedance and external voltage divider setup into section 6.1
Circuit .
1.5 10 Jan 2014
Updated TOC with correct page numbers.
Added noted regarding smartBASIC firmware’s lack of support for GPIO high
drive state.
1.6 06 Feb 2014 Updated Bluetooth SIG Qualification section.
1.7 18 Feb 2014 Updated Operating temperature range
1.8 04 April2014
Updated or added the following for the BL600-Sx-04:

Lower power consumption figures (standby doze, deep sleep) and lower
peripheral (UART, SPI, I2C, ADC) block currents for the BL600-Sx-04
(new Nordic silicon).

Improved UART with deep RX buffer (6 bytes instead of 2 bytes).

Increased the Absolute Max rating on the VCC pin from 3.6V to 3.9V.

Added a note for External 12K resistor to GND on SWDCLK pin NOT
required on BL600-Sx-04.
Added the following for all BL600 module revisions to align with FW features:

Section on PWM output and FREQ output signals.

Note on GPIO high drive strength (5 mA).

Note regarding internal DCDC convertor turned OFF on
recommendation from chipset supplier until further notice. Updated
Peak current consumption figures with DCDC turned OFF (with internal
LDO ON).

Added in the pin list the newly FW (1.5.66.0, April 2014) enabled
internal pull-ups to prevent inputs from floating and to help with the
issue of Standby Doze current drifting with time.