26
I/O Terminal /
MANUAL CONFIGURATION
Feature bit no.
Mode Description
1 1
4-fold evaluation of the encoder signals
A, B, C
Bit 14 – 12
0
Reserved, don’t change
Bit 15
0/1
0: Encoder interface. [0]
1: Counter mode is activated.
16-bit up/down counter
Input A: Counter
Input B: Counting direction (5 V or open
= up, 0 V= down)
Input C: Latch
5.6 Register
Communication
Register Access Via Process Data Exchange | Bit 7=1bin: Register Mode
If bit 7 of the control byte is set, then the first two bytes of the user data are not used for
exchanging process data, but are written into or read from the terminal's register set.
Bit 6=0
bin
: read | Bit 6=1
bin
: write
Bit 6 of the control byte specifies whether a register should be read or written. If bit 6 is not set,
then a register is read out without modifying it. The value can then be taken from the input
process image.
If bit 6 is set, then the user data is written into a register. As soon as the status byte has supplied
an acknowledgement in the input process image, the procedure is completed (see example).
Bit 0 to 5: Address
The address of the register that is to be addressed is entered into bits 0 to 5 of the control byte.
5.6.1 Control Byte in Register Mode
7
6
5
4
3
2
1
0
Bit
name
REG = 0
W/R
A5
A4
A3
A2
A1
A0
REG = 0bin: Process data exchange
REG = 1bin: Access to register structure
W/R = 0bin: Read register
W/R = 1bin: Write register
A5...A0 = register address
Address bits A5 to A0 can be used to address a total of 64 registers.
