I/O Terminal /
MANUAL CONFIGURATION
Conditions
Word offset
High byte
Low byte
0
–
CB/SB
1
D0
D1
2
–
D2
Complete evaluation: any
Motorola format: yes
Word alignment: yes
3
D3
D4
Key
Complete evaluation: The terminal is mapped with control / status byte.
Motorola format: The Motorola or Intel formal can be set.
Word alignment: The terminal is at a word limit in the bus coupler.
CB: Control- Byte (appears in the process image of the outputs).
SB: Status- Byte (appears in the process image of the inputs).
D0/D1: Counter word (read/set)
(D2): contains the period, together with 3/D4
D3/D4: Latch word (read)
5.2
Control and Status Byte
The following section describes the control and status bytes.
5.2.1 Control Byte in Process Transfer
The control byte is transferred from the controller to the terminal. It can be used in the register
mode (REG = 1) or in process data transfer (REG = 0). Various actions are triggered in the AKT-
ENC-000-000 with the control byte:
7
6
5
4
3
2
1
0
Bit
name
REG =
0
-
-
-
En_Latch_Ext_n
Cnt_Set
EN_LAT_EXT/
RD_PERIOD
EN_LATC
Bit
Bit
Function
3
En_Latch_Ext_n
The external latch input is activated for
negative edge. With the first external
latch impulse after validity of the
EN_Latch_Ext_n bit, the counter value
in the latch register is stored. The
pulses that follow have no influence on
the latch register when the bit is set.
Attention must be paid to ensuring that
the corresponding latch valid bit
(Latch_Ext_Val) has been removed
from the terminal before alerting of the
zero pulse. This functionality is
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