Koheron Alpha250 User Manual Download Page 14 | Manualshive

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Summary of Contents for Alpha250

Page 1: ...e 12V jack of the power supply The power good green LED PWGD and the FPGA done orange LED DONE indicate the system has correctly started Communicating with the board LAN The ethernet port is the main communication interface with the Alpha250 It can be connected to a local network via a router support tutorials nd dynamic ip or directly to a computer support tutorials setup direct ethernet static i...

Page 2: ...e expansion connector Maximum current is 3 A protected by an electronic fuse USB 2 0 This is a USB 2 0 host connector It provides up to 1 A current at 5 V shared with the 5 V supply of the expansion connector The power and data pins are ESD protected Micro USB 2 0 Connects to the UART0 PS core via a FTDI device It is used as a debugging serial interface The power and data pins are ESD protected Gi...

Page 3: ...st be driven from VCCIO_3V3 both for voltage compliance and power sequencing Applying non compliant voltages on these pins may result in SoC failure Two LVDS clocks from the clocking subsystem EXP_CLK0 and EXP_CLK1 4 user IOs from the GPIO expander USER_IOx Voltage level is 3 3 V They can be con gured as inputs or outputs open drain or pull up These I Os have 22 Ω series protection resistors They ...

Page 4: ...ble data rate The maximum transfer rate per LVDS pair is thus 500 Msps The transfer protocol is described in the LTC2157 14 datasheet https cds linear com docs en datasheet 21576514fb pdf A clock synchronous with the data ADC_CLKOUT is also connecting the Bank 34 The RF ADC is con gured by the con guration SPI bus The source code of the corresponding C driver is on GitHub https github com Koheron ...

Page 5: ...e reference clock sources are The CLKI SMA input on the board It is a 50 Ω impedance input that accepts an AC voltage of up to 2 5 V 10 dBm It also supports up to 5 V An onboard precision high speed comparator 890 Mbps provides effective clock recovery It is ESD protected The FPGA_CLK_OUT signal to discipline the system on a clock provided by the FPGA The onboard 10 MHz temperature compensated vol...

Page 6: ...on DAC is a 4 channel 16 bit DAC Analog Devices AD5686 http www analog com media en technical documentation data sheets AD5686_5684 pdf The output voltage ranges from 0 to 2 5 V It includes an output buffer that can deliver up to 20 mA per channel The outputs are ESD protected Alpha250 Precision DAC interface The four output channels are available on the expansion connector Communication with the ...

Page 7: ...d the clocking subsystem supply In both cases the current shunt resistor is 10 mΩ Both power monitors are accessible on the I2C0 bus via the PowerMonitor driver https github com Koheron koheron sdk blob master boards alpha250 drivers power monitor hpp EEPROM The Alpha250 has a 64 kbit EEPROM Microchip 24AA64T I MC http ww1 microchip com downloads en DeviceDoc 21189K pdf It is accessible on the I2C...

Page 8: ...0x1000 0x100 EEPROM map addressing Zynq I Os The Zynq XC7Z020 2CLG400I has 2 I O banks for the programmable logic Banks 34 and 35 with 48 IOs each One bank Bank 0 is dedicated to the processing system with a multiplexed I O MIO interface The set of peripherals and interface buses is depicted below Zynq peripherals and communication buses I O constraints are de ned in the ports xdc le https github ...

Page 9: ...operty PACKAGE_PIN N17 get_ports adc_0_p 4 set_property PACKAGE_PIN W20 get_ports adc_0_n 5 set_property PACKAGE_PIN V20 get_ports adc_0_p 5 set_property PACKAGE_PIN U20 get_ports adc_0_n 6 set_property PACKAGE_PIN T20 get_ports adc_0_p 6 Channel 1 set_property PACKAGE_PIN W13 get_ports adc_1_n 0 set_property PACKAGE_PIN V12 get_ports adc_1_p 0 set_property PACKAGE_PIN Y14 get_ports adc_1_n 1 set_...

Page 10: ... get_ports dac_0 15 Channel 1 set_property PACKAGE_PIN F20 get_ports dac_1 0 set_property PACKAGE_PIN F19 get_ports dac_1 1 set_property PACKAGE_PIN J16 get_ports dac_1 2 set_property PACKAGE_PIN K16 get_ports dac_1 3 set_property PACKAGE_PIN G20 get_ports dac_1 4 set_property PACKAGE_PIN G19 get_ports dac_1 5 set_property PACKAGE_PIN K18 get_ports dac_1 6 set_property PACKAGE_PIN K17 get_ports da...

Page 11: ...he bits B2 and B3 of the cmd byte according to the table below N1 N0 Description 0 0 Transfer one byte 0 1 Transfer two bytes 1 0 Transfer three bytes 1 1 Transfer four bytes Con guration SPI byte transfer count The chip select address is speci ed using the bits B0 and B1 of the cmd byte according to the table below A1 A0 Description 0 0 CS 0 0 1 CS 1 1 0 CS 2 Con guration SPI chip select address ...

Page 12: ...get_ports spi_precision_dac_ set_property PACKAGE_PIN V17 get_ports spi_precision_dac_cs set_property PACKAGE_PIN V18 get_ports spi_precision_dac_sck set_property PACKAGE_PIN T17 get_ports spi_precision_dac_sdi set_property PACKAGE_PIN R18 get_ports spi_precision_dac_ldac Transfer core While the valid is high the core updates the DAC channels with the values on pin data The 64 bits of the data pin...

Page 13: ...r supply monitor 1000101 Clocking subsystem supply monitor 1001000 Voltage reference temperature sensor 1001001 Board temperature sensor 0101111 TCXO control voltage I2C1 The I2C1 bus is for the expansion connector A 3 3 V level shifter with 2 2 kΩ pull ups provides the interface with the Bank 0 The I2C1 core can be replaced by a CAN core CAN0 with proper PS con guration ENET0 The ethernet periphe...

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