Koheron Alpha250, User Manual

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4 precision DAC outputs. Outputs from the 16-bit precision DAC.
Subsystems
RF ADC
The RF Analog-to-Digital Converter has 2 acquisition channels with 14-bit resolution and 250 Msps maximum sampling rate (Linear
Technologies LTC2157-14 (https://cds.linear.com/docs/en/datasheet/21576514fb.pdf)). It has two inputs labeled IN0 and IN1 on
the SMA connectors. The inputs are DC coupled and 50
Ω
terminated. The optimum DC offset is reached when the input is driven
from a 50
Ω
output impedance source. The peak-peak input range is 1 V (between -500 and 500 mV). The inputs are protected by
a transient voltage suppressor clamping over-voltages beyond ± 8 V.
Alpha250 RF ADC interface.
The encoding clock of the ADC is provided by the
RF_ADC_CLK
of the clocking system. The output data are interfaced to the I/O
Bank 34 of the FPGA. It consists of 14 LVDS pairs operating in double data rate. The maximum transfer rate per LVDS pair is thus
500 Msps. The transfer protocol is described in the LTC2157-14 datasheet
(https://cds.linear.com/docs/en/datasheet/21576514fb.pdf). A clock synchronous with the data
ADC_CLKOUT
is also connecting the
Bank 34.
The RF ADC is con gured by the con guration SPI bus. The source code of the corresponding C++ driver is on GitHub
(https://github.com/Koheron/koheron-sdk/blob/master/boards/alpha250/drivers/ltc2157.hpp).
RF DAC
The RF Digital-to-Analog Converter has 2 outputs with 16-bit resolution and 250 Msps maximum sampling rate (Analog Devices
AD9747 (http://www.analog.com/media/en/technical-documentation/data-sheets/AD9743_9745_9746_9747.pdf)). The outputs
are labeled OUT0 and OUT1 on the SMA connectors. Output impedance is 50
Ω
. The outputs are protected by a transient voltage
suppressor clamping over-voltages beyond ± 8 V.
The output range is 1.5 V maximum in a 50
Ω
load. It can be adjusted using the DAC gain on the con guration SPI bus. In the
default con guration, the DAC outputs 1 V in a 50 Ω load.
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