Koheron Alpha250, User Manual

Page: 11 / 14

# Configuration SPI (Bank 34)
set_property IOSTANDARD LVCMOS18 [get_ports spi_cfg_*]
set_property PACKAGE_PIN R17 [get_ports spi_cfg_sdo]
set_property PACKAGE_PIN R16 [get_ports spi_cfg_sdi]
set_property PACKAGE_PIN W16 [get_ports spi_cfg_sck]
set_property PACKAGE_PIN V16 [get_ports spi_cfg_cs_rf_adc]
set_property PACKAGE_PIN U12 [get_ports spi_cfg_cs_rf_dac]
set_property PACKAGE_PIN T12 [get_ports spi_cfg_cs_clk_gen]
Transfer core
The core is write only. It does not read back con gurations from the chips. The
s_axis_tready
signal can be used to determine
when the core nishes sending a message and is ready to send a new one.
The core can send 1, 2, 3 or 4 bytes of data. The number of bytes to transfer is speci ed using the bits
B2
and
B3
of the
cmd
byte
according to the table below.
N1 N0 Description
0 0 Transfer one byte
0 1 Transfer two bytes
1 0 Transfer three bytes
1 1 Transfer four bytes
Con guration SPI byte transfer count.
The chip select address is speci ed using the bits
B0
and
B1
of the
cmd
byte according to the table below.
A1 A0 Description
0 0
CS
= 0
0 1
CS
= 1
1 0
CS
= 2
Con guration SPI chip select address.
The transferred data must be wired to the
s_axis_tdata
pin. The transfer is triggered on the
s_axis_tvalid
pin falling edge. The
core is controlled via the SpiCon g driver (https://github.com/Koheron/koheron-sdk/tree/master/boards/alpha250/drivers/spi-
con g.hpp).
Precision ADC SPI bus
A dedicated SPI is used for the communication with the precision ADC. The bus is connected to PL I/Os on bank 34.
Precision ADC SPI bus.
Constraint le
The precision ADC SPI pins are connected to the Bank 34 with 1.8 V LVCMOS signals.