Koheron Alpha250, User Manual

Page: 10 / 14

# RF DAC (Bank 35)
set_property IOSTANDARD LVCMOS33 [get_ports dac_*]
set_property DRIVE 8 [get_ports dac_*]
set_property IOSTANDARD LVCMOS33 [get_ports dac_*]
set_property DRIVE 8 [get_ports dac_*]
# Channel 0
set_property PACKAGE_PIN D18 [get_ports {dac_0[0]}]
set_property PACKAGE_PIN E17 [get_ports {dac_0[1]}]
set_property PACKAGE_PIN E19 [get_ports {dac_0[2]}]
set_property PACKAGE_PIN E18 [get_ports {dac_0[3]}]
set_property PACKAGE_PIN A20 [get_ports {dac_0[4]}]
set_property PACKAGE_PIN B19 [get_ports {dac_0[5]}]
set_property PACKAGE_PIN F17 [get_ports {dac_0[6]}]
set_property PACKAGE_PIN F16 [get_ports {dac_0[7]}]
set_property PACKAGE_PIN B20 [get_ports {dac_0[8]}]
set_property PACKAGE_PIN C20 [get_ports {dac_0[9]}]
set_property PACKAGE_PIN L17 [get_ports {dac_0[10]}]
set_property PACKAGE_PIN L16 [get_ports {dac_0[11]}]
set_property PACKAGE_PIN D20 [get_ports {dac_0[12]}]
set_property PACKAGE_PIN D19 [get_ports {dac_0[13]}]
set_property PACKAGE_PIN G18 [get_ports {dac_0[14]}]
set_property PACKAGE_PIN G17 [get_ports {dac_0[15]}]
# Channel 1
set_property PACKAGE_PIN F20 [get_ports {dac_1[0]}]
set_property PACKAGE_PIN F19 [get_ports {dac_1[1]}]
set_property PACKAGE_PIN J16 [get_ports {dac_1[2]}]
set_property PACKAGE_PIN K16 [get_ports {dac_1[3]}]
set_property PACKAGE_PIN G20 [get_ports {dac_1[4]}]
set_property PACKAGE_PIN G19 [get_ports {dac_1[5]}]
set_property PACKAGE_PIN K18 [get_ports {dac_1[6]}]
set_property PACKAGE_PIN K17 [get_ports {dac_1[7]}]
set_property PACKAGE_PIN H20 [get_ports {dac_1[8]}]
set_property PACKAGE_PIN J20 [get_ports {dac_1[9]}]
set_property PACKAGE_PIN M18 [get_ports {dac_1[10]}]
set_property PACKAGE_PIN M17 [get_ports {dac_1[11]}]
set_property PACKAGE_PIN H18 [get_ports {dac_1[12]}]
set_property PACKAGE_PIN J18 [get_ports {dac_1[13]}]
set_property PACKAGE_PIN G15 [get_ports {dac_1[14]}]
set_property PACKAGE_PIN H15 [get_ports {dac_1[15]}]
Con guration SPI bus
A shared SPI bus is dedicated to the con guration of the RF ADC, the RF DAC and the clock generator. In the reference design, a
HDL core is used for the communication on this bus. The interface is described below.
Con guration SPI bus.
Constraint le
The con guration SPI bus pins are connected to Bank 34 with 1.8 V LVCMOS signals.