# Precision ADC (Bank 34)
set_property IOSTANDARD LVCMOS18 [get_ports spi_precision_adc_*]
set_property PACKAGE_PIN U13 [get_ports spi_precision_adc_cs]
set_property PACKAGE_PIN V13 [get_ports spi_precision_adc_sck]
set_property PACKAGE_PIN T11 [get_ports spi_precision_adc_sdi]
set_property PACKAGE_PIN T10 [get_ports spi_precision_adc_sdo]
Data transfer
In the reference design, the precision ADC SPI bus is connected to the SPI0 PS core. This is done using the EMIO interface which
allows to connect PL signals to the MIO interface of the PS. It can be controlled using the PrecisionAdc driver
(https://github.com/Koheron/koheron-sdk/tree/master/boards/alpha250/drivers/precision-adc.hpp).
Precision DAC SPI bus
Data is transferred to the precision DAC using a SPI bus that can be clocked up to 50 MHz. In addition, a latched pin
LDAC
pin is used
to update the 4 channel outputs synchronously. In the reference design, a dedicated HDL core is used. The interface is shown below.
Precision DAC SPI bus.
Constraint le
The precision DAC SPI pins are connected to the Bank 34 with 1.8 V LVCMOS signals.
# Precision DAC (Bank 34)
set_property IOSTANDARD LVCMOS18 [get_ports spi_precision_dac_*]
set_property PACKAGE_PIN V17 [get_ports spi_precision_dac_cs]
set_property PACKAGE_PIN V18 [get_ports spi_precision_dac_sck]
set_property PACKAGE_PIN T17 [get_ports spi_precision_dac_sdi]
set_property PACKAGE_PIN R18 [get_ports spi_precision_dac_ldac]
Transfer core
While the
valid
is high, the core updates the DAC channels with the values on pin
data
. The 64 bits of the
data
pin contain the
concatenation of the 4 x 16 bits values to be set on the 4 channels. Channel 0 being on the 16 least signi cant bits, followed by
channels 1, 2 and 3. After sending the data for the 4 channels, the core latches
ldac
. The data will be synchronously updated if
cmd
= 3, the output is updated as new values arrive. The core (https://github.com/Koheron/koheron-
sdk/tree/master/boards/alpha250/cores/precision_dac_v1_0) is written in Verilog. It is controlled with the PrecisionDac driver
(https://github.com/Koheron/koheron-sdk/tree/master/boards/alpha250/drivers/precision-dac.hpp).
PS cores
The processing system contains hard cores (by opposition with the soft cores that can be deployed on the PL). The PS cores are
interfaced with MIO pins on Bank 0. The logic level is LVCMOS 1.8 V. MIO con guration can be found in the board con guration le
(https://github.com/Koheron/koheron-sdk/tree/master/boards/alpha250/con g/board_preset.tcl).
Summary of Contents for Alpha250
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