25
N5250A Millimeter-Wave PNA Block Diagram
Reference
receiver
Reference
receiver
Option 016
receiver
attenuators
Port 1
Port 2
Bias-tee
50 dB
A
Bias-tee
50 dB
B
R1
R2
LO distribution to
each receiver
To IF multiplexer
(see Figure 5)
To IF multiplexer
(see Figure 5)
LO: 2 to 20 GHz
R1
IF
R2
IF
A
IF
B
IF
R1
gate
R2
gate
A
gate
B
gate
RF: 2 to 20 GHz
IF multiplexer
A/D
External
IF input
IF gating
RF
LO
(from LO distribution.
See test set
block diagram)
SMA
connectors
BNC
connectors
SMA
connectors
BNC
connectors
50 dB
50 dB
Receiver A
Receiver B
Port 1
Port 2
67 to 110 GHz
waveguide head
67 to 110 GHz
waveguide head
IF1 IF2
IF3
IF4
Test set I/O
LO
RF
Combiner assembly
Test
port 1
Test
port 2
E8361A
with Option H11
N5260A
with
test heads
30 in.
76.2 cm
48 in.
121.9 cm
30 in.
76.2 cm
48 in.
121.9 cm
Combiner assembly
Optional
bias-tees
(Option 017)
Test set controller
PNA test set block diagram
Simplified receiver block diagram
With Option 017, the signal is routed out of
the PNA from the front panel jumpers rather
than the ports. Without Option 017, the
signal is routed from the front panel ports to
the combiner assembly, allowing access to
the PNA’s internal bias-tees.
