TK-373G
12
CIRCUIT DESCRIPTION
Fig. 4
AF Amplifier and Squelch
Fig. 5 PLL circuit
5) Audio amplifier circuit
The demodulated signal from IC4 is amplified by IC16 (2/2),
high-pass filtered, low-pass filtered, high-pass filtered, band-
eliminate filtered, and de-emphasized by IC14.
The signal then goes through an AF amplifier IC15 (2/2), an
AF volume control (VR2), and is routed to an audio power
amplifier (IC11) where it is amplified and output to the speaker.
6) Squelch
Part of the AF signal from the IC enters the FM IC (IC4)
again, and the noise component is amplified and rectified
by a filter and an amplifier to produce a DC voltage
corresponding to the noise level.
The DC signal from the FM IC goes to the analog port of
the microprocessor (IC13). IC13 determines whether to
output sounds from the speaker by checking whether the
input voltage is higher or lower than the preset value.
To output sounds from the speaker, IC6 sends a high signal
to the SP MUTE line and turns IC11 on through
Q32,Q33,Q34 and Q30. (See Fig. 4)
7) Receive signaling
QT/DQT/LTR
300Hz and higher audio frequencies of the output signal from
IF IC are cut by a low-pass filter (IC19). The resulting signal
enters the microprocessor (IC13). IC13 determines whether
the QT, DQT or LTR matches the preset value, and controls
the SP MUTE and the speaker output sounds according to
the squelch results.
DET
IC13
IF AMP
IC16 (2/2)
IF AMP
IC19
LPF
QT/DQT/LTR
93
ANSQL
TOI
95
FM IF IC4
5
43
Q36
SW
Q32, 33, 34
SW
DE-
EMP
MUTE
EXP
HPF
LPF
HPF
BEF
IC14
2
1
IC15 (2/2)
AF AMP
41
IC11
AF PA AMP
Q30
SW
SP
OUTPUT EXPANDER
IC6
5RC
SP
MUTE
5
7
CPU
PLL DATA
16.8MHz
REF OSC
1/M
1/N
PLL IC IC2
PHASE
COMPARATOR
CHARGE
PUMP
LPF
10kHz/12.5kHz
D2, 4
D9, 11
Q37,38
Q2
TX VCO
Q10
RX VCO
Q3
BUFF AMP
Q4
RF AMP
Q1
X2 multiply
Q7, 8
T/R SW
10kHz/12.5kHz
3. PLL frequency synthesizer
The PLL circuit generates the first local oscillator signal for
reception and the RF signal for transmission.
1) PLL
The VCO output is doubled by Q1 and then sent to the PLL
IC (IC2).
The frequency step of the PLL circuit is 10 or 12.5kHz.
A 16.8MHz reference an oscillator signal is divided at IC2
by a fixed counter to produce oscillator (VCO) output signal
which is buffer amplified by Q3 then divided in IC2 by a
dual-module programmable counter. The divided signal is
compared in phase with the 10 or 12.5kHz reference signal
from the phase comparator in IC2. The output signal from
the phase comparator is filtered through a low-pass filter
and passed to the VCO to control the oscillator
frequency.(See Fig. 5)
2) VCO
The operating frequency is generated by Q2 in transmit
mode and Q10 in receive mode. The oscillator frequency is
controlled by applying the VCO control voltage, obtained
from the phase comparator, to the varactor diodes (D2 and
D4 in transmit mode and D9 and D11 in receive mode).
The T/R pin is set high in receive mode causing Q7 and Q8
to turn Q2 off and turn Q10 on.
The T/R pin is set low in transmit mode. The outputs from
Q10 and Q2 are amplified by Q3 and sent to the buffer
amplifiers.
3) Unlock Detector
If a pulse signal appears at the LD pin of IC2, an unlock
condition occurs, and the DC voltage obtained form D1,
R1, and C6 causes the voltage applied to the microprocessor
to go low. When the microprocessor detects this condition,
the transmitter is disabled, ignoring the push-to-talk switch
input signal.(See Fig. 6)
Fig. 6 Unlock detector circuit
IC2
LD
PLL IC
D1
C6
R1
5C
IC13
UL
MPU
