Theory of Operation
6-10
Adapter), while U119 and U120 are 75160 and 75161 inter-
face bus drivers.
The 9914 GPIA simplifies MPU interfacing to the IEEE-488
bus because many control sequences take place automatical-
ly. For example, when the MPU writes to the GPIA data out-
put register, the handshake sequence is performed
automatically. Without the GPIA chip, complex firmware
routines would otherwise be required.
On the MPU side of the GPIA, data transmission is handled
much like any other data bus transaction. MPU data access is
performed through the D0-D7 lines, while the RS0-RS2
lines (which are connected to the three least significant ad-
dress lines) serve to select among the 14 internal registers
(seven read, seven write) of the IC. Chip selection is per-
formed by the CS line.
The output of the 9914 IC is in standard IEEE-488 format;
the eight data lines (DIO1-DIO8), the three handshake lines
(DAV, NRFD, NDAC), and the five management lines (ATN,
REN, IFC, SRQ, and EOI) are all active low with approxi-
mately zero volts representing a logic one. The two IEEE-
488 bus drivers, U119 and U120, are necessary to bring the
drive capability of the interface up to the requirements of the
IEEE-488 standard, which includes provisions for up to 15
devices to be connected to the bus at one time. The outputs
of the bus drivers are connected to J1010, which is a standard
IEEE- 488 connector.
6.6.5 Input/output circuitry
Additional MPU functions include the control of the Meter
Complete Output and External Trigger Input, and analog-to-
digital converter control.
At the end of its conversion cycle, the Model 6512 sends a
pulse out the Meter Complete Output jack on the rear panel.
This function is performed by the PB2 line of the MPU
through U102A configured as a buffer/inverter. Diodes CR104
and CR105 and resistor R102 protect the circuit output.
U102D, U105B, and associated components process the in-
coming trigger signal. U102D buffers and inverts the signal,
while U105B latches the trigger pulse. The pulse is then read
by the MPU through PA6. PB1 is used to reset the trigger
latch once the pulse is read. Note that PB1 is also used to
read the status of the calibration jumper (W101) during the
calibration program.
As with the Meter Complete Output, protection of the Exter-
nal Trigger Input is necessary to protect the device from
over-voltage inputs. External Trigger protection components
include R101, CR102, and CR103.
A/D control information is fed out the PB3 and PB5 termi-
nals through U102B. A pulse-width modulation scheme is
used, with 18 and 50µsec pulses representing logic 0 and
logic 1 respectively. A 200µsec pulse is used to strobe data
into the A/D and serial-parallel control circuits. Note that this
information is used to control the A/D converter as well as to
control the input preamplifier (through relays), set the rang-
ing amplifier gain, and to control the three phases of the mea-
surement cycle. Isolation is provided by opto-isolator U122.
Because of this isolation scheme, input signal common can
be floated up to ±500V above chassis ground, while digital
common floats within ±30V of ground.
In a similar fashion, A/D data is routed in from the A/D con-
verter through opto-isolator U121. The MPU reads this data
through the TIMER terminal. As data pulses come in, an in-
ternal 8-bit timer is incremented until 256 counts have oc-
curred. When all counts have been taken, an internal
interrupt is generated, which causes to MPU to read the timer
data. A separate firmware counter is then decremented, and
the process repeats. Because of this data input scheme, MPU
time necessary to read the A/D converter data is minimized,
and the processor can concentrate on other important tasks.
6.6.6 Display circuitry
Display circuitry includes those elements necessary to con-
trol the seven- and 14-segment readouts, the front panel an-
nunciator LEDs, and to read the front panel switches. The
display circuitry schematic may be found on drawing num-
ber 6512-116 located at the end of Section 8.
The display circuitry consists of the LED readouts (DS201-
DS206), the LED annunciators (DS207-DS224), the seg-
ment drivers (U201 and U202), and the digit select circuitry
(U204, U201, and U203). DS202-DS205 are standard 7-seg-
ment units, while DS206 is a dual 14-segment display.
The display is updated at 1.56msec intervals. Timing for this
process is performed by a 640Hz clock, which controls the
segment latches, U110 and U116, located on the mother
board. Each time an interrupt is generated, the MPU writes
segment data for two digits to the segment latches. The two
latch outputs are then enabled in sequence by the 640Hz
Summary of Contents for 6512
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