Komodo Fiber Reference Guide
38
8.1.1
DDR3 memories
The reference design uses two DDR3 controllers from Altera to interface the onboard DDR3 bank
and the SODIMM bank. For the SODIMM bank, the controller is configured to work with
MT8KTF51264HZ-1G6E1 SODIMM from Micron.
Both the controllers are configured in Quarter rate (512bit) Avalon interface and operate at 533
MHz clock rate. The onboard DDR3 controller is configured as OCT (On Chip Termination)
sharing master, while the SODIMM controller as slave.
The DDR3 controllers are driven by Altera Avalon-MM Traffic Generator IPs that performs a
memory test after board reset.
The status of the memory test can be seen on board LEDs D3 and D4 for Onboard and SODIMM
banks respectively. If the LED is lit the test have passed. The test status signals are also pulled to
Signal TAP and In System Sources and Probes IP.
For more information about the DDR3 controller and traffic generator please visit Altera
documentation at
http://www.altera.com/literature/lit-external-memory-interface.jsp
.
8.1.2
PCI Express
The PCI Express incorporates Altera hard IP configured in Gen2 x8 lanes mode. The IP is
connected to internal FPGA SRAM. The SRAM can be read and written from the PC.
The PCI Express status signals are pulled to Signal TAP DS1 LED indicates that the PCI Express IP
have entered L0 state.
For more information about the PCI Express IP please see Altera documentation at
http://www.altera.com/literature/ug/ug_a5gz_pcie_avmm.pdf
.
The access to the PCIe from PC can be made using JINGO driver that should be downloaded
separately from
http://www.jungo.com/st/products/windriver/
.
KAYA instruments also offers PCI Express Gen3 x8 IP, High performance Scatter Gather DMA IP
and a Drivers for DMA and PCI Express both for Windows and Linux. For IP licensing options
please contact KAYA Instruments representative.
8.1.3
Ethernet PHY
For QSFP+ and SFP+ demonstration, Altera 10GBase-R PHY is used. The PHY is configured to 8
ports and connected both to SFP+ and QSFP+ modules. The XGMII side of the PHY is connected
to KAYA traffic generator and tester. The traffic generator is an open source IP that generates and
Reference Design
