Komodo Fiber Reference Guide
17
Board
reference (J1)
Signal Name
Arria V
GZ Pin
Number
I/O Standard
Description
1
rout[0]
AH26
3.3-V LVTTL
Pin 1 of this header is the positive
signal and pin 2 in the negative
signal of this LVDS. The
differential pair is converted to a
single input on the FPGA
2
3
rout[1]
AK28
3.3-V LVTTL
Pin 3 of this header is the positive
signal and pin 4 in the negative
signal of this LVDS. The
differential pair is converted to a
single input on the FPGA
4
5
din[0]
AK27
3.3-V LVTTL
Pin 5 of this header is the positive
signal and pin 6 in the negative
signal of this LVDS. The
differential pair is converted to a
single output on the FPGA
6
7
din[1]
AM26
3.3-V LVTTL
Pin 7 of this header is the positive
signal and pin 8 in the negative
signal of this LVDS. The
differential pair is converted to a
single output on the FPGA
8
9
io_out[0]
AF26
3.3-V LVTTL
Optically isolated outputs
10
io_out[1]
AE26
3.3-V LVTTL
Optically isolated outputs
11
io_out[2]
AD26
3.3-V LVTTL
Optically isolated outputs
12
io_out[3]
AC26
3.3-V LVTTL
Optically isolated outputs
13
io_in[0]
U26
3.3-V LVTTL
Optically isolated inputs
14
io_in[1]
Y25
3.3-V LVTTL
Optically isolated inputs
15
io_in[2]
W25
3.3-V LVTTL
Optically isolated inputs
16
io_in[3]
V25
3.3-V LVTTL
Optically isolated inputs
17
OptoCoupled
GND
-
-
Ground signal for opto-isolated
signals on this connector
18
GND
-
-
Reference ground signal - Board
GND
19
gpio_vt[0]
AM11
TTL
General Purpose IO
20
gpio_vt[1]
AL11
TTL
21
gpio_vt[2]
AM10
TTL
22
gpio_vt[3]
AL10
TTL
23
gpio[0]
AA30
3.3-V LVTTL
24
gpio[1]
AE28
3.3-V LVTTL
25
gpio[2]
AD28
3.3-V LVTTL
26
gpio[3]
AB27
3.3-V LVTTL
Table 3: General purpose Inputs and outputs pin assignments, signal name and functions
Board Components