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Komodo Fiber Reference Guide

Board

reference

Signal Name

Arria V

GZ Pin

Number

Arria V

GZ Clock

Name

I/O

Standard

Description

cxp_clkp

REFCLK0Rp

LVDS

125 MHz oscillator for

transceiver reference clock

cxp_clkn

REFCLK0Rn

U29

clk25[0]

AE16

CLK7p

SSTL-135

25 MHz oscillators for DDR3

memory

U33

clk25[1]

J19

CLK19p

J17

pcie_refclk_p

U28

REFCLK1Lp

HCSL

100 MHz clock coming from

the PCI express edge connector

pcie_refclk_n

U29

REFCLK1Ln

U51

eth_clkp

REFCLK2Rp

LVDS

322.265625 MHz oscillator for

transceiver reference clock

eth_clkn

REFCLK2Rn

U52

eth_opt_clkp

REFCLK1Lp

LVDS

Optional 322.265625 MHz

oscillators for transceiver

reference clock

eth_opt_clkn

REFCLK1Ln

Table 2: Clocks pin assignments, signal name and functions

I/O and Transceivers

The Komodo Fiber utilizes several I/O banks out of the possible 26 I\O or transceiver banks
available on the Arria V GZ FPGA. The following figure describes what each bank is used for:

B2R

B0R

B1R

B2L

B0L

B1L

QSFP

transceirers

SFP+

PCIe_Tx

PCIe_Rx

DDR3 SDRAM + SFP and QSFP I/O + GPIO

DDR3 SODIMM

Figure 5: I/O and transceiver usage

Board Components

Summary of Contents for Komodo Fiber

Page 1: ...ber Reference Guide Part No KY FGF 5 201 June 20 aMesila St Nesher 3688520 Israel P O B 2 50 0 4 Ha i fa 3 125 0 0 1 I s r a e l Tel 972 72 2723500 Fax 972 72 2723511 w w w k a y a i n s t r u m e n t...

Page 2: ...iew of the Board 12 Komodo Fiber Board components 13 Featured device Arria V GZ FPGA 13 FPGA Configuration 14 4 6 1 FPGA configuration via JTAG 14 4 6 2 FPGA configuration via on board flash memory 14...

Page 3: ...ages 33 Power rails 33 Electrical characteristics for board IO s 34 Top Level Example Design 36 Reference Design 37 Functional block diagram 37 8 1 1 DDR3 memories 38 8 1 2 PCI Express 38 8 1 3 Ethern...

Page 4: ...URE 16 KOMODO FIBER WITH LOOPBACK FIXTURES 41 Tables TABLE 1 KOMODO FIBER BOARD COMPONENTS 13 TABLE 2 CLOCKS PIN ASSIGNMENTS SIGNAL NAME AND FUNCTIONS 15 TABLE 3 GENERAL PURPOSE INPUTS AND OUTPUTS PIN...

Page 5: ...PUT DC SPECIFICATIONS DRIVER OUTPUTS 34 TABLE 17 LVDS INPUT DC SPECIFICATIONS RECEIVER INPUTS 34 TABLE 18 LVTTL INPUT SPECIFICATIONS 35 TABLE 19 LVTTL OUTPUT SPECIFICATIONS 35 TABLE 20 TTL INPUT SPECI...

Page 6: ...the product Otherwise a fire or electric shock may occur due to a short circuit or heat generation For inspection modification or repair contact our sales personnel Do not touch a cooling fan As a coo...

Page 7: ...y be damaged Disclaimer Even if the product is used properly KAYA Instruments assumes no responsibility for any damages caused by the following Earthquake thunder natural disaster or fire resulting fr...

Page 8: ...to external devices The QSFP and SFP interfaces are connected directly to FPGA device transceiver channels to minimize latency All of these features combine make the Komodo Fiber ideal for a wide ran...

Page 9: ...er Transfer Rate of up to 60 Gbps through PCIe Transfer Rate of up to 80 Gbps through optical interfaces CWDM support QSFP can be expanded to 4x 10G interfaces Temperature control Fan control 4 indica...

Page 10: ...Komodo Fiber Reference Guide 9 Related documents and accessories Documents Komodo Fiber Reference Guide Reference design Accessories SFP module QSFP module GPIO extension panel Key Features...

Page 11: ...rcuitry JTAG header EPCQ256 programmable flash memory Clocking circuitry Two 322 265625 MHz LVDS oscillator for transceiver reference clock 1 of them is optional 125 MHz LVDS oscillator for transceive...

Page 12: ...e LED dual color Power supply PCI Express edge connector power Board Block diagram GPIO PCIe 3 0 8 up to 64 Gbps QSFP Bank A DDR3 64 16 Gb 4 green user LEDs Bank B DDR3 64 up to 128 Gb Oscillators JTA...

Page 13: ...Komodo Fiber Reference Guide 12 External View of the Board Figure 2 Komodo Fiber front view Figure 3 Komodo Fiber back view Board Components...

Page 14: ...oscillator 322 265625 MHz oscillators for transceiver reference clock Memory devices U14 U18 U22 U26 DDR3 x64 memory 16Gb DDR3 SDRAM with 64 bit data bus The 64 bit data bus consists of 4 x16 devices...

Page 15: ...memory Upon the power up the FPGA tries to fetch the configuration from that flash The EPCQ256 flash can be programmed using an external USB Blaster device with the Quartus II Programmer running on a...

Page 16: ...llator for transceiver reference clock eth_clkn R5 REFCLK2Rn U52 eth_opt_clkp U7 REFCLK1Lp LVDS Optional 322 265625 MHz oscillators for transceiver reference clock eth_opt_clkn U6 REFCLK1Ln Table 2 Cl...

Page 17: ...r Reference Guide 16 4 8 1 General purpose I O The Komodo Fiber supports 20 different I O connections on the FPGA as described in Figure 6 and Table 3 Figure 6 General purpose Inputs and outputs Board...

Page 18: ...gnal of this LVDS The differential pair is converted to a single output on the FPGA 8 9 io_out 0 AF26 3 3 V LVTTL Optically isolated outputs 10 io_out 1 AE26 3 3 V LVTTL Optically isolated outputs 11...

Page 19: ...a connection speed of 2 5 Gbps lane for a maximum of 20 Gbps full duplex Gen1 or 5 0 Gbps lane for a maximum of 40 Gbps full duplex Gen2 or 8 0 Gbps lane for a maximum of 64 Gbps full duplex Gen3 The...

Page 20: ...pcie_tx_p 4 Y31 1 5 V PCML A36 pcie_tx_n 4 Y32 1 5 V PCML A39 pcie_tx_p 5 V31 1 5 V PCML A40 pcie_tx_n 5 V32 1 5 V PCML A43 pcie_tx_p 6 T31 1 5 V PCML A44 pcie_tx_n 6 T32 1 5 V PCML A47 pcie_tx_p 7 P3...

Page 21: ...le J11 If any or both of those memories are used the RZQ signal must be connected to the DDR3 control IP If only the on board DDR3 memory is used this signal should be connected to the DDR3 IP that co...

Page 22: ...l is connected to the master DDR3 controller and the through it also connected to the slave DDR3 controller as shown in Figure 9 SODIMM DDR3 DDR3 IP Slave on board DDR3 DDR3 IP Master RZQ sharing enab...

Page 23: ...O Standard Description Common control signals to all four on board SDRAMs N3 ddr3_2_a 0 AC14 1 35 V SSTL Address bus P7 ddr3_2_a 1 AD15 1 35 V SSTL P3 ddr3_2_a 2 W21 1 35 V SSTL N2 ddr3_2_a 3 AG12 1...

Page 24: ...STL A7 ddr3_2_dq 39 AN15 1 35 V SSTL H3 ddr3_2_dq 56 AD16 1 35 V SSTL F2 ddr3_2_dq 57 W15 1 35 V SSTL G2 ddr3_2_dq 58 W16 1 35 V SSTL F7 ddr3_2_dq 59 AG16 1 35 V SSTL H8 ddr3_2_dq 60 W17 1 35 V SSTL F...

Page 25: ..._2_dq 7 AH23 1 35 V SSTL G2 ddr3_2_dq 24 AF18 1 35 V SSTL H8 ddr3_2_dq 25 W18 1 35 V SSTL E3 ddr3_2_dq 26 AF19 1 35 V SSTL F2 ddr3_2_dq 27 AG18 1 35 V SSTL F7 ddr3_2_dq 28 AA18 1 35 V SSTL H7 ddr3_2_d...

Page 26: ...x16 devices with a single address or command bus This interface support rates of up to 1066 MT s This interface connects to the vertical I O banks on the top edge of the FPGA Board reference J11 Signa...

Page 27: ..._dm 5 D19 1 35 V SSTL Write mask byte 5 63 ddr3_1_dm 6 D22 1 35 V SSTL Write mask byte 6 136 ddr3_1_dm 7 F27 1 35 V SSTL Write mask byte 7 177 ddr3_1_dq 0 J27 1 35 V SSTL Data bus 163 ddr3_1_dq 1 L27...

Page 28: ...54 E23 1 35 V SSTL 70 ddr3_1_dq 55 E24 1 35 V SSTL 141 ddr3_1_dq 56 E26 1 35 V SSTL 143 ddr3_1_dq 57 F26 1 35 V SSTL 129 ddr3_1_dq 58 H28 1 35 V SSTL 142 ddr3_1_dq 59 E28 1 35 V SSTL 132 ddr3_1_dq 60...

Page 29: ...smit receive data at rates of up to 10Gb and the QSFP module can transmit receive data at rates of up to 40Gb Board reference JP1 Signal Name Arria V GZ Pin Number I O Standard Description 27 qsfp_mod...

Page 30: ...AK10 2 5 V Serial I2C clock line 4 sfp_sda 2 W9 2 5 V Serial I2C data line 6 sfp_presn 2 AN25 3 3 V LVTTL Reset active low 3 sfp_tx_dis 2 AD7 2 5 V Transmitter Disable 7 sfp_rs_rx 2 AN6 2 5 V Received...

Page 31: ...d reference Signal Name Arria V GZ Pin Number I O Standard Description D11 sfp_led_greenn 3 AH10 2 5 V Open drain User defined LEDs intended for showing transmit or receive activity on the SFP module...

Page 32: ...I O as described in the following table Board reference J6 Signal Name Arria V GZ Pin Number I O Standard Description 1 fan_ctrl AG24 3 3 V LVTTL User controlled fan output Driving logic 1 on the I O...

Page 33: ...d mechanical dimensions are as defined in Figure 11 For more detailed information please contact KAYA Instruments representative Figure 11 PCB Mechanical Dimensions Absolute maximum ratings Specificat...

Page 34: ...0 slot 3 3 3 0 9 12 0 5 5 66 Table 13 Power input Maximum and minimum input voltages The minimum and maximum input voltages that the Komodo Fiber can endure are based on PCIe standard and shown in the...

Page 35: ...plementary Output States 1 25 mV IOS Output Short Circuit Current 4 ENABLED DIN VDD DOUT 0 V or DIN GND DOUT 0 V 5 8 9 0 mA IOSD Differential Output Short Circuit Current 4 ENABLED VOD 0 V 5 8 9 0 mA...

Page 36: ...t Low Voltage VDD min IOL 2 mA 0 4 V Vdd 3 3V unless specified otherwise Table 19 LVTTL output specifications Symbol Parameter Test condition MIN MAX Units VIH Input High Voltage VOUT VOH min or VOUT...

Page 37: ...level example design contains all the required project settings and an empty top level design for KOMODO Fiber in Verilog and VHDL The top level design files can be found under fpga_top_level folder...

Page 38: ...interface each for onboard DDR3 bank and an SODIMM bank The controller for the SODIMM bank is configured to use MT8KTF51264HZ 1G6E1 SODIMM module from Micron In addition to DDR3 memories the referenc...

Page 39: ...ra com literature lit external memory interface jsp 8 1 2 PCI Express The PCI Express incorporates Altera hard IP configured in Gen2 x8 lanes mode The IP is connected to internal FPGA SRAM The SRAM ca...

Page 40: ...ollow the following steps 1 Make sure Quartus II is installed on your PC 2 Install KOMODO Fiber board into the PC 3 Connect the USB Blaster cable or USB Blaster II cable to the KOMODO Fiber board and...

Page 41: ...y to KAYA Instruments Please contact KAYA Instruments representative for availability of the fixtures For SFP loopback optical SFP loopback fixtures are required Figure 13 shows the optical SFP loopba...

Page 42: ...ke sure Quartus II is installed on your PC 2 Install KOMODO Fiber board into the PC 3 Connect the USB Blaster cable or USB Blaster II cable to the KOMODO Fiber board and host PC Install the USB Blaste...

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