JYTEK PCIe-69834 User Manual Download Page 18 | Manualshive

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8

Introduction

Figure 1-3: PCIe-

69834

I/O Array

All I/O connectors are SMB snap-on.

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Summary of Contents for PCIe-69834

Page 1: ...PCIe 69834 4CH 16 bit 80MS s Digitizer PCIe 69834 PCIe 69834P User s Manual Manual Rev 2 00 Revision Date June 3 2016 Part No 50 11263 1000...

Page 2: ...ii Revision History Revision Release Date Description of Change s 2 00 June 3 2016 Initial Release...

Page 3: ...even if advised of the possibility of such damages Environmental Responsibility JYTEK is committed to fulfill its social responsibility to global environmental preservation through compliance with th...

Page 4: ...asks CAUTION Information to prevent minor physical injury component dam age data loss and or program corruption when trying to com plete a task Information to prevent serious physical injury component...

Page 5: ...al Specifications 5 1 4 Software Support 5 1 4 1 WD DASK 6 1 5 Device Layout and I O Array 7 2 Getting Started 11 2 1 Installation Environment 11 2 2 Installing the Module 12 3 Operations 13 3 1 Funct...

Page 6: ...with Re Triggering 20 3 5 Timebase 21 3 5 1 Internal Sampling Clock 22 3 5 2 External Reference Clock PCIe 69834P only 22 3 6 ADC Timing Control 23 3 6 1 Timebase Architecture 23 3 6 2 Basic Acquisiti...

Page 7: ...Trigger Mode Acquisition 19 Figure 3 7 Pre Trigger Mode Acquisition 20 Figure 3 8 Middle Trigger Mode Acquisition 20 Figure 3 9 Re Trigger Mode Acquisition 21 Figure 3 10 PCIe 69834 Clock Architecture...

Page 8: ...viii List of Figures This page intentionally left blank...

Page 9: ...Table 3 1 Input Range and Data Format 14 Table 3 2 Input Range FSR and FSR Values 14 Table 3 3 Input Range Midscale Values 15 Table 3 4 Counter Parameters and Description 25 Table 3 5 SSI Signal Locat...

Page 10: ...x List of Tables This page intentionally left blank...

Page 11: ...up to 1GB the PCIe 69834 easily manages simultaneous 4 CH data streaming even at the highest sampling rates The PCIe 69834 is auto calibrated with an onboard reference cir cuit calibrating offset and...

Page 12: ...nput Item Spec Notes Channels 4 single ended Connector type SMB Input coupling DC ADC resolution 16 Bit Input range 0 5 V 1 V 5V or 10V 10V only supported Input impedance 1M Bandwidth 3dB 40MHz Overvo...

Page 13: ...nel Bandwidth Gain Error 0 15 System Noise RMS 0 1mV 0 5V 0 15mV 1V 1mV 5V 1 5 mV 10 V Crosstalk 80 dB 0 5 V 90 dB 1 V or 5V or 10V SNR 67 dB THD 78 dB SFDR 78 dB Item Spec Notes 7 6 5 4 3 2 1 0 1 1 0...

Page 14: ...z H M 0 1 External reference clock input range 3 3V to 5V TTL DC compliant Trigger Source Mode Trigger source Software external digital trigger analog trigger and SSI system synchronized interface Tr...

Page 15: ...cifications Dimensions 167 64 W x 106 68 H mm 6 53 x 4 16 in Bus interface PCI Express Gen 1 x 4 Operating Temperature 0 C 50 C Relative humidity 5 95 non condensing Storage Temperature 20 C 80 C Rela...

Page 16: ...ealer to purchase the software license 1 4 1 WD DASK WD DASK includes device drivers and DLL for Windows XP 7 8 10 DLL is binary compatible across Windows XP 7 8 10 This means all applications develop...

Page 17: ...Introduction 7 1 5 Device Layout and I O Array Figure 1 2 PCIe 69834 Schematic The PCIe 69834 I O array is labeled to indicate connectivity as shown NOTE NOTE All dimensions are in mm...

Page 18: ...8 Introduction Figure 1 3 PCIe 69834 I O Array All I O connectors are SMB snap on...

Page 19: ...xt Digital Trigger TRG External digital trigger input receiving trigger signal from external instrument and initiating acquisition Ext Reference Clock Input REF_CLK PCIe 69834P with PLL module only RE...

Page 20: ...10 Introduction This page intentionally left blank...

Page 21: ...lat and cross head screwdrivers preferably with magnetic heads as screws and standoffs are small and easily misplaced Recommended Installation Tools Phillips cross head screwdriver Flat head screwdriv...

Page 22: ...ss slot on the back panel Slowly push down on the top of the PCI express digitizer until its card edge connector is resting on the slot receptacle 5 Install the bracket retaining screw to secure the P...

Page 23: ...ration Figure 3 1 Analog Input Architecture Input Configuration The input channel terminates with equivalent 50 or 1M input impedance selected by software The 16 bit ADC provides CH0 CH1 CH2 CH3 CLK I...

Page 24: ...ference voltage to the AI 3 2 2 Input Range and Data Format Data format of the PCIe 69834 is 2 s complement Table 3 1 Input Range and Data Format Table 3 2 Input Range FSR and FSR Values D15 D14 D13 D...

Page 25: ...ta to a user defined DMA buffer in the computer Using a high level programming library for high speed DMA data acquisition the sampling period and the number of conversions needs simply to be assigned...

Page 26: ...Each descriptor contains a PCI address PCI dual address a transfer size and the pointer to the next descrip tor PCI address and PCI dual address support 64 bit addresses which can be mapped into more...

Page 27: ...e trigger generated by software command is asserted immediately following execution of specified function calls to begin the operation 3 3 2 External Digital Trigger An external digital trigger is gen...

Page 28: ...t occurs The following trig ger mode descriptions are applied to analog input function 3 4 1 Post Trigger Mode Post trigger acquisition is applicable when data is to be collected after the trigger eve...

Page 29: ...unter value such that a maximum thereof is the period of TIMEBASE X 216 and the minimum is the Timebase period Figure 3 6 Delayed Trigger Mode Acquisition 3 4 3 Pre Trigger Mode Collects data before t...

Page 30: ...taining N R samples channel of data without additional software intervention The Re Trigger setting can be used for Post Trigger and Delayed Trigger modes with different limitations on the spacing bet...

Page 31: ...Post Trigger mode the minimum spacing between trigger events is N 1 In Delayed Trigger mode the minimum spacing between trigger events is N D 1 where D is the number of the delayed setting Figure 3 9...

Page 32: ...act as an external reference clock input such that when multi card synchronization for more than two modules is needed a 10MHz clock source can be provided to REF_CLK and API function utilized to swit...

Page 33: ...oun ter is used Using the post trigger mode as an example as shown when a trigger is accepted by the digitizer the acquisition engine com mences acquisition of data from ADC and stores the sampled dat...

Page 34: ...6 66MS s and vice versa The scan interval counter is 16 bits in width therefore the lowest sampling rate is 1 221kS s 80MS s 65535 Figure 3 13 Varying Sampling Rates by Adjusting Scan Interval Counter...

Page 35: ...ference clock should be applied Counter Name Length Valid Value Description ScanIntrv 16 bit 1 65535 Timebase divider to achieve equivalent sampling rate of the digitizer where Sampling rate Timebase...

Page 36: ...nd Pin Definition 3 7 1 Card Number Configuration When multiple cards are used in a single chassis card number configuration via switch as shown NOTE NOTE Different signals cannot be routed onto the s...

Page 37: ...in ON position card number is 15 when all are OFF card number is 0 as shown Slider 1 Slider 2 Slider 3 Slider 4 Card OFF OFF OFF OFF 0 OFF OFF OFF ON 1 OFF OFF ON OFF 2 OFF OFF ON ON 3 OFF ON OFF OFF...

Page 38: ...rmware updates If firm ware updates fail the system may be unable to recognize the module in which case the following steps may solve the problem 1 Config SW2 to on 2 Install the module and restart th...

Page 39: ...iguration Switch 3 9 Measurement Function API The PCIe 69834 supports measurement function APIs for easily conversion of basic voltage time measurement results with no extra programming required for d...

Page 40: ...n Lowest waveform value Refer to Figure 3 16 Waveform Transition Double V mean Arithmetic average value of the waveform Waveform i n Double V p2p Peak to peak max min Double V std Standard deviation W...

Page 41: ...ints of a negative waveform pulse Double Sec poswidth Positive pulse width the duration between two consecutive mid reference level points of a positive waveform pulse Double Sec negdutycycle Negative...

Page 42: ...value of the waveform high value wd_hist _bin V low Voltage low calculated via histogram using the voltage of the histogram bin with the maximum number of hits below 40 of the peak to peak value of th...

Page 43: ...ge high amplitude 100 Double negovershoot Peak distortion following a valid negative transition voltage low local min amplitude 100 Double cyclemean Arithmetic average of integral number of points in...

Page 44: ...34 Operations This page intentionally left blank...

Page 45: ...e calibration constants are recorded to Bank 1 When PCIe 69834 boots the driver accesses the calibration con stants and is automatically set to hardware In the absence of user assignment the driver lo...

Page 46: ...es and remove connected cables Figure A 1 Auto Calibration Block Diagram NOTE NOTE It is not necessary to manually factor delay into applications as the PCIe 69834 driver automatically adds the compen...

Page 47: ...re data and calculate offset compensation parameters Are all channels and all ranges complete No Set calibration source to calibration voltage Capture data and calculate gain compensation parameters Y...

Page 48: ...38 Calibration This page intentionally left blank...

Page 49: ...rn off power and unplug any power cords cables To avoid electrical shock and or damage to equipment Keep equipment away from water or liquid sources Keep equipment away from high heat or high humidity...

Page 50: ...be serviced by authorized technicians when The power cord or plug is damaged Liquid has penetrated the equipment It has been exposed to high humidity moisture It is not functioning or does not functi...

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