JYTEK PCIe-69834, User Manual

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24 Operations
Figure 3-12: Basic Digitizer Acquisition Timing
To achieve sampling rates other than 80MS/s, a number for scan
interval counter needs only be specified. For example, if the scan
interval counter is set as 2, the equivalent sampling rate is 80MS/s
/ 2 = 40MS/s. If as 3, the equivalent sampling rate is 80MS/s / 3 =
26.66MS/s, and vice versa. The scan interval counter is 16 bits in
width, therefore the lowest sampling rate is 1.221kS/s (80MS/s /
65535).
Figure 3-13: Varying Sampling Rates by Adjusting Scan Interval Counter
ADC
X6
Multiplier
PLL
For ADC
State machine
For ADC
Data Bus
80MHz
480MHz
FPGA
ADC Output
80MHz
Onboard
80MHz
Oscillator
TIMEBASE
DATA
D1
Acquisition
In Progress
Trigger
Acquisition is initiated following this clock edge
D1
ScanIntrv = 1
D2 D3
D4
D5
D6
D7 D8 D9
D10
D2 D3 D4 D5 D6
D1
D2 D3 D4
ScanIntrv = 2
ScanIntrv = 3