JYTEK PCIe-69834, User Manual

Page: 23 / 50

Operations 13
3 Operations
This chapter contains information regarding analog input,
trigger-ing and timing for the PCIe-
69834
.
3.1 Functional Block Diagram
3.2 Analog Input Channel
3.2.1 Analog Input Front-End Configuration
Figure 3-1: Analog Input Architecture
Input Configuration
The input channel terminates with equivalent 50 Ω or 1M Ω input
impedance (selected by software). The 16-bit ADC provides
CH0
CH1
CH2
CH3
CLK IN
REF_CLK
TRIG IN
Analog
Front-End
Calibration
16 Bit ADC
P
C
Ie Inter
face
FPGA
SSI
Clock
Distribution
Calibration
Source
50
Ÿ
/Hi-Z High Impedance
Buffer
Attenuator
Anti-
aliasing
Filter
0
0
0
0
0
16
16-bit ADC
ADC Driver