JBL MS-8 Service Manual Download

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M_LRCLK

I2S_IN1

ADC_MCLK

M_BCLK

ADC_MCLK

SYSCLK
DSP_MCLK
ADC_MCLK
DAC_MCLK

ADC_PDN#

I2S_IN2

I2S_IN3

I2S_IN0

M_BCLK

M_LRCLK

C182
10uF

C196

10uF

C195

10uF

C147

2.2uF

C299
0.1uF

U16D

74HCU04

C187

10uF

C336
0.1uF

U16A

74HCU04

R299

C228

10uF

C114

10uF

C167

10uF

C172

2.2uF

C192

10uF

C112

2.2uF

5x5.7XCO

INH

GND

Output

VCC

Y1
ASSVP-24.576MHZ-C04-T

U16C

74HCU04

C333

0.1uF

VDD

GND

VEE

U15

74HC4052

C335

0.1uF

U16F

74HCU04

TSSOP16

AINR

AINL

CKS1

VCOM

AGND

DGND

SDTO

LRCK

MCLK

SCLK

PDN

DIF

CKS2

CKS0

U14
AK5358ET

C334

0.1uF

C111

10uF

C206

2.2uF

R294

C197

10uF

C203

0.1uF

C169

10uF

C337

0.1uF

C125

10uF

R296

C116

10uF

C207

0.1uF

C148
10uF

C171

10uF

C229

10uF

TSSOP16

AINR

AINL

CKS1

VCOM

AGND

DGND

SDTO

LRCK

MCLK

SCLK

PDN

DIF

CKS2

CKS0

U13
AK5358ET

R174
10k

C332

0.1uF

U16B

74HCU04

C198

10uF

R295

TSSOP16

AINR

AINL

CKS1

VCOM

AGND

DGND

SDTO

LRCK

MCLK

SCLK

PDN

DIF

CKS2

CKS0

U5
AK5358ET

C146

10uF

U16E

74HCU04

C300

0.1uF

C210

0.1uF

R320

R321

C227

10uF

C222
10uF

TSSOP16

AINR

AINL

CKS1

VCOM

AGND

DGND

SDTO

LRCK

MCLK

SCLK

PDN

DIF

CKS2

CKS0

U6
AK5358ET

AGND

3P3V

AGND

3P3V

AGND

DGND

3P3V

DGND

AGND

+5VA

3P3V

DGND

3P3V

DGND

3P3V

I2S_IN[3:0]

LIN2

RIN2

LIN3

RIN3

RIN4

LIN4

MUX0

DAC_MCLK

SYSCLK

DSP_MCLK

ADC_PDN#

MicL_analog

MicR_analog

LIN1

RIN1

MUX1

AUX_R

AUX_L

M_BCLK

M_LRCLK

Keep PDN low unti l pow eran d clo ck s hav e stabilize d

This resistor is lo cat edcl os e t o the A K5358

This re si sto r is lo catedcl os e to the AK53 58

MCLK = 24.576 MHz
BCLK = 3.072 MHz
LRCLK = 48 kHz

CH1

CH5

CH2

CH6

CH3

CH7

CH4

CH8

The resistor n etw or k should be close t o the 74HCU04 chip

These r es ist or s are locat edclose t o the A K53 58

Use daisy-chain routing
(not tree routing) for
the M_BCLK and M_LRCLK
signals. The
termination resistors
should be at one end of
the chain.

DW GNO:

PART NO:

PART NAME:

PRODUCT MODE:

SCALE: 1:1

UNIT: MM

SIZE:

REV:

DRAWN BY:

CHECKED BY:

APPROVED BY:

DATA:

DESCRIPTON

DATA

APPROVED

DESCRIPTON

REV

Place

DATA

EVR

ADC

MS-8 MAIN AMP

ChengHao

2009.09.08

Sheet 8 of 18

6
6

2,9

2
2

1
2
3
4

RN10

33X4

I2S_IN0

I2S_IN1
I2S_IN2
I2S_IN3

3P3V

M_AIN_R

M_AIN_L

3P3V

MS-8

Summary of Contents for MS-8

Page 1: ...MS 8 8 Channel System integration digital processor SERVICE MANUAL JBL Consumer Products 8500 Balboa Blvd Northridge CA 91329 Rev0 5 2010 Released 2010 Discontinued XXXX ...

Page 2: ...utput 85dB Maximum Input Voltage Speaker Level Input 15V Maximum Input Voltage Line Input 2 8V Maximum Output Voltage Line Output 2 8V Maximum Current Draw 16A Standby Current Draw 0 01A Display LCD Screen 128 x 64 pixels Power Requirement 12V DC negative ground Main Unit Dimensions L x W x H 11 1 2 x 7 3 8 x 2 1 8 293mm x 187mm x 55mm Display Unit Dimensions H x W x D w stand 3 1 8 x 3 3 8 x 2 7 ...

Page 3: ...MS 8 PACKAGING LITHIUM COIN BATTERY 3VDC CR2032 MS 8 2 ...

Page 4: ...al controls not found on conventional car audio amplifiers Also the calibration setup and usage for the MS 8 is unique Details can be found in the MS 8 owner s manual which can be downloaded here http www jbl com EN US Products Pages ProductDetails aspx PID MS 8 accT 1 tsT 0 ovT 0 click on link then on Grey tab SUPPORT MS 8 3 ...

Page 5: ... gauge wire for this connection English CONNECTIONS REMOVE FOR SOFTWARE UPDATE 25A fuse Mic connection Lineinput connections HiLevelinput Remoteout connection Speakeroutput connections Lineoutput connections Auxinput connections Display connection Power LED Reset button Update connection 12V connection Remotein connection GND connection Chassis ground unpainted 5 CONNECTIONS MS 8 4 ...

Page 6: ...t the amplifier If your factory amplifier has a turn on wire cut it and connect the head unit side of the wire to the MS 8 s Rem In terminal and the amplifier side of the wire to the MS 8 s Rem Out terminal This arrangement will allow the factory stereo to turn the MS 8 on whenever the stereo is turned on and will allow the MS 8 to turn the factory amplifier on and off It will also help to elimina...

Page 7: ...UDIO INPUTS Many factory installed systems include on board equalization and crossovers that make simple connection of aftermarket products difficult The MS 8 includes the signal summing circuitry signal conditioning EQ and time correction processing that are necessary to reconstruct a flat full range two channel signal when you use the MS 8 with factory installed equipment Aftermarket head units ...

Page 8: ...line inputs 3 8 During the calibration setup process the MS 8 will normalize the input signals and derive as many output signals as your speaker system requires IMPORTANT Do not connect the head unit directly to any amplifiers including a subwoofer amplifier The MS 8 s signal processing takes nearly 8ms so any signals connected directly to a head unit will be ahead of the signals leaving the MS 8 ...

Page 9: ...nd does not represent any particular vehicle audio system Insert the included Hi Level input wiring harness into the MS 8 s Hi Level input connector until it locks into place IMPORTANT The MS 8 s Hi Level input wiring harness has gray and white wires Each channel has a white positive or wire and a gray negative or wire Each wire is labeled with its channel number and polarity and is pre stripped f...

Page 10: ...yer as an auxiliary audio source unit connect its line or headphone output to the MS 8 s Aux input using a cable that terminates in stereo RCA audio connections You can switch between the MS 8 s Head Unit inputs and Aux input in the MS 8 s Input Selection menu See Main Menu on page 35 10 CONNECTIONS MS 8 9 ...

Page 11: ...han eight channels use additional separate amplifiers connected to the MS 8 s line outputs for the additional channels For example if you want to build a 7 1 channel system that includes bi amped or tri amped front speakers use the MS 8 to generate the 7 1 channel outputs seven full range and one subwoofer Connect the MS 8 s front line outputs to the inputs of an additional crossover or amplifier ...

Page 12: ...ive your system s speakers connect the speakers to the MS 8 s speaker outputs Insert the included speaker output wiring harness into the MS 8 s speaker output until it locks into place See Main Menu on page 35 IMPORTANT The MS 8 s speaker output wiring harness s wires have clear insulation Each channel has a copper positive or conductor and a silver negative or conductor We have labeled each condu...

Page 13: ...ay use the MS 8 s amplifer OR an outboard amplifier but not both Be sure to use the chart above to note which speakers are connected to which MS 8 channels Leftfront Tweeter Leftfront midrange Leftrear coaxial Not used Speakeroutput wiringharness Subwoofer amplifier Lineoutput 6 Not used Rightrear coaxial Subwoofer Rightfront midrange Rightfront Tweeter Vehicle Speaker System 13 CONNECTIONS MS 8 1...

Page 14: ...ing additional outboard power amplifiers to drive your system s speakers connect their inputs to the MS 8 s line output connectors You can power some of the system s speakers by the MS 8 s amplifiers and some by outboard amplifiers but you should use only one connection type per output For example Output Channel 1 may use the MS 8 s amplifier OR an outboard amplifier but not both Be sure to use th...

Page 15: ... If the display unit is disconnected after setup and final adjustment you will not be able to make any additional MS 8 adjustments and the remote control will not function See Main Menu on page 35 MICROPHONE The included binaural microphone headset must be connected to the MS 8 s Mic connection during the calibration setup process Once setup is complete unplug the microphone headset and store it i...

Page 16: ...until you are ready to install a firmware upgrade that you will download from www JBL com 16 CONNECTIONS MS 8 RESETTING THE MICROPROCESSOR If the MS 8 stops responding to the remote control even after you ve replaced the remote s battery or fails to operate in the way this manual describes use a pen or similar pointed object to press the Reset button on the main unit NOTE Pressing this Reset butto...

Page 17: ...elects or otherwise changes the state of a highlighted item Back menu button Momentarily pressing this button causes the display to revert to the next higher menu Holding the button reverts to your default screen either the Main Menu or Audio Controls screen from whatever screen is active at the time See Default Screen on page 40 Mute button Press to mute the sound press again to restore the sound...

Page 18: ...ee Input Selection Menu on page 35 Perform the calibration setup procedure The procedure must be performed before the MS 8 will pass an audio signal through to its outputs See Calibration Setup on page 24 Confirm that all the required channels of the source unit are properly connected See Audio Inputs on page 7 The 12V Gnd or Rem In terminals are not properly connected The fuse is blown The displa...

Page 19: ... document which speakers are connected to which MS 8 Confirm that the speaker is connected to the correct MS 8 speaker output or to the correct outboard amplifier channel Improper input connection Improper output connection Improper speaker connection to outboard amplifier Outboard amplifier channel is not functioning Troubleshoot the outboard amplifier and replace it if necessary Confirm that the...

Page 20: ... 8 s System Volume at 20dB If you have connected the front speakers to an external higher powered amplifier that is connected to the MS 8 s line outputs set the MS 8 s System Volume to a level lower than 20dB In either case you should use the head unit s volume control to control the system s volume You may need to make a minor adjustment to the MS 8 s System Volume setting to allow you to use mor...

Page 21: ...he calibration setup process again with the MS 8 s System Volume set at 20dB See Acoustic Calibration on page 32 Use the MS 8 s Audio Controls menu to activate Logic 7 and DSP See on page 36 The MS 8 s Tone Controls and or Graphic EQ are mis adjusted Use the MS 8 s Tone Controls and or Graphic EQ screens to return all controls to their center positions See Audio Controls Menu on page 36 Use the MS...

Page 22: ...e displays only once and the MS 8 resets without incident no further involvement is necessary If the message displays often contact JBL Technical Support at 516 255 4JBL 4525 Re install the main unit in a less confined area that will allow cooling air to circulate around the unit See Choosing a Location for the Main Unit on page 17 TROUBLESHOOTING MISCELLANEOUS The display is hard to read The Brig...

Page 23: ... Bottom 1 9 W LS1BM0040081 Screw BM4 8 3 10 W LS1AY0401201 Screw PM4 12 4 11 W JD B40600515 Thermally conductive Pad 3 12 W ZA H00010101 Bracket 2 13 W LS1KM0040071 Screw KM4 7 8 14 W LS1AJ0301001 Screw PA3 10 9 15 W ZA B00130100 IC Bracket B 1 16 W SR MS80 0325 SUB Heatsink B 1 17 W LS1BE0301607 Screw BM3 16 6 18 W LS1AY0300601 Screw PM3 6 9 19 W ZL 10002A 35 LED Spacer 1 20 Main PCB 1 MS 8 EXPLO...

Page 24: ... Autosense and Microcontroller SWITCH 5V_DISP To Display LCD uC RFReceiver AUX PRE AMP Sheet 11 AUDIOAUTOSENSE Sheet 14 L 4 1 R 4 1 L 4 1 R 4 1 NOTE Unless otherwise specifed all non polarized capacitors are ceramic 0603 package 50V or higher and 10 tolerance Unless otherwise specified all resistors are 0603 package 5 tolerance PROPRIETARY INFORMATION THESE DOCUMENTS AND THE INFORMATION CONTAINED ...

Page 25: ...DUCT MODE SCALE 1 1 UNIT MM SIZE REV DRAWN BY CHECKED BY APPROVED BY DATA DATA DATA DESCRIPTON DATA APPROVED DESCRIPTON REV REV Place Place DATA Block Diagram MS 8 AUTO DSP DISPLAY T4 ChengHao 2010 04 03 Sheet 2 of 3 B LCD TRANSCEIVER nRF24L01 M25P80 3 3V SPI RF FLASH FLASH nRF24L01 MICROCONTROLLER LCD LED LED MS 8 24 ...

Page 26: ...T MM SIZE REV DRAWN BY CHECKED BY APPROVED BY DATA DATA DATA DESCRIPTON DATA APPROVED DESCRIPTON REV REV Place Place DATA Block Diagram MS 8 AUTO DSP RF CONTROLLER T4 ChengHao 2010 04 03 Sheet 3 of 3 B TRANSCEIVER nRF24L01 BATTERY RF POWER 3VDC CR2032 PCBLOOP ANTENNA UP DOWN LEFT RIGHT SELECT MENU MUTE VOLUMET VOLUMET MS 8 25 ...

Page 27: ...1 0603 61 R29 R31 R32 R33 R37 R40 R43 R45 R46 R50 R54 R57 R58 R61 R62 R65 R66 R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 R89 R91 R103 R158 R167 R169 R173 R174 R186 R187 R189 R198 R199 R201 R205 R208 R211 R214 R217 R220 R223 R226 R229 R230 R233 R283 R284 R298 R382 R383 R34 R39 R297 W 0701 1243 03 Resistor SMD 24KΩ 1 10W 1 0603 1 R9 W 0701 1203 03 Resistor SMD 20KΩ 1 10W 1 0603 9 R254 R256 R257 R25...

Page 28: ...0 Capacitor SMD 104 100V 0603 X7R 10 1 C1 W 06S111046002 Capacitor SMD 104 50V 0603 X7R 10 90 C27 C29 C126 C127 C128 C149 C150 C170 C174 C181 C188 C189 C190 C193 C199 C203 C207 C210 C215 C216 C217 C218 C219 C230 C234 C236 C238 C239 C249 C252 C253 C254 C255 C273 C274 C275 C276 C277 C279 C280 C299 C300 C301 C303 C304 C314 C315 C316 C317 C318 C319 C320 C321 C323 C326 C327 C328 C329 C330 C331 C332 C33...

Page 29: ...15 Diode SMD BAV70 SOT 23 NXP 12 D1 D4 D6 D8 D10 D11 D13 D15 D17 D25 D27 D29 W 03T1 AW56 04 Diode SMD BAW56 SOT 23 11 D3 D5 D7 D9 D12 D14 D16 D18 D26 D28 D30 W 04WY BZX8 15 Diode SMD BZX84C3V9 ZENER 3 9V SOT 23 1 D24 W 04XT RS06 00 Diode SMD CRS06 Schottky Barrier Rectifier 1 D22 W 04WY 56AV100 Diode SMD 5 6V SC 74A FTZ5 6E 5pins ROHM 2 DP2 DP3 W 03T0 358P 04 Mos FET SMD FDN358P P Ch Logic Level E...

Page 30: ... WR 2 Jacks 4 PINS white and red 1 J11 W 1501 0800 00 Jack DIP 39 30 1160 3 96 8P 2 J3 J6 W 1503 0700 00 needle stand TM 2008 AG 14 2 54 14P double 7P 1 J9 W 1401 0004 00 Fuse holder BXS 09 1 for F1 W 1601 253G 01 Fuse DIP 25A 32V LittelFuse 1 F1 W 1003 0004 08 Inductor SMD 1NH 0805 0 3NH 6 L17 L18 L19 L21 L23 L24 W 1003 1500 00 Inductor SMD 15uH 5 2A SMRH74 150M 1 L22 W 18SM 2400 00 Crystal SMD A...

Page 31: ...MS 8 30 Top layer ...

Page 32: ...MS 8 31 Power layer ...

Page 33: ...MS 8 32 Inner l3 layer ...

Page 34: ...MS 8 33 Inner l4 layer ...

Page 35: ...MS 8 34 Bottom layer ...

Page 36: ...MS 8 35 ...

Page 37: ...MS 8 36 ...

Page 38: ...bility Options Marking Configuration 2 Meg x 32 512K x 32 x 4 banks 2M32B2 Plastic package OCPL1 86 pin TSOP II 400 mil TG 86 pin TSOP II 400 mil Pb free P 90 ball VFBGA 8mm x 13mm Pb free B5 Timing cycle time 5ns 200 MHz 5 5 5ns 183 MHz 55 6ns 166 MHz 6 7ns 143 MHz 7 Die revision G Operating temperature range Commercial 0 to 70 C None Industrial 40 C to 85 C IT2 Automotive 40 C to 105 C AT3 Notes...

Page 39: ...EAD DATA LATCH WRITE DRIVERS COLUMN DECODER BANK0 MEMORY ARRAY 2 048 x 256 x 32 BANK 0 ROW ADDRESS LATCH DECODER 2048 SENSE AMPLIFIERS BANK CONTROL LOGIC DQ0 DQ31 32 32 DATA INPUT REGISTER DATA OUTPUT REGISTER 32 BANK 1 BANK 0 BANK 2 BANK 3 11 8 2 4 4 2 REFRESH COUNTER 11 11 MODE REGISTER CONTROL LOGIC COMMAND DECODE ROW ADDRESS MUX ADDRESS REGISTER COLUMN ADDRESS COUNTER LATCH MS 8 38 ...

Page 40: ... DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC CLK CKE A9 A8 A7...

Page 41: ...SSQ DQ11 DQ13 DQ24 VDDQ DQ27 DQ29 DQ31 DQM3 A5 A8 CKE NC DQ8 DQ10 DQ12 VDDQ DQ15 VSS VSSQ DQ25 DQ30 NC A3 A6 NC A9 NC VSS DQ9 DQ14 VSSQ VSS VDD VDDQ DQ22 DQ17 NC A2 A10 NC BA0 CAS VDD DQ6 DQ1 VDDQ VDD DQ21 DQ19 VDDQ VDDQ VSSQ VDD A1 NC RAS DQM0 VSSQ VDDQ VDDQ DQ4 DQ2 DQ23 VSSQ DQ20 DQ18 DQ16 DQM2 A0 BA1 CS WE DQ7 DQ5 DQ3 VSSQ DQ0 A B C D E F G H J K L M N P R MS 8 40 ...

Page 42: ...e CS is HIGH CS provides for external bank selection on systems with multiple banks CS is considered part of the command code 17 18 19 K8 K7 J9 WE CAS RAS Input Command inputs WE CAS and RAS along with CS define the command being entered 16 71 28 59 K9 K1 F8 F2 DQM0 DQM3 Input Input output mask DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read ...

Page 43: ... manner Operational procedures other than those specified may result in undefined operation After power is applied to VDD and VDDQ simultaneously and the clock is stable stable clock is defined as a signal cycling within timing constraints specified for the clock pin the SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND INHIBIT or NOP Starting at some point during this...

Page 44: ...L command 7 Wait at least t RP time during this time 0 NOPs or DESELECT commands must be given All banks will complete their precharge thereby placing the device in the all banks idle state 8 Issue an AUTO REFRESH command 9 Wait at least t RFC time during which only NOPs or COMMAND INHIBIT commands are allowed 10 Issue an AUTO REFRESH command 11 Wait at least t RFC time during which only NOPs or C...

Page 45: ...External Memory Interface EMIF Seamlessly Expands Memory Space by Supporting SRAM SDRAM FLASH EPROM and SBSRAM Four External Address Spaces D 16 Bit Host Port Interface HPI Enables High Speed Encode Decode Applications D Enhanced Direct Memory Access EDMA Controller With 16 Independent Channels D Two Multichannel Audio Serial Ports McASPs Independent Dual Zone Audio on a Single DSP 16 Data Pins 32...

Page 46: ...0 CVDD EA17 VSS VSS VSS DVDD EMU2 VSS DVDD CVDD DVDD VSS VSS CVDD CVDD DVDD VSS CVDD CVDD DVDD VSS EA21 BE1 VSS VSS CVDD CVDD RSV VSS EMU0 CLKOUT3 CVDD OSCIN VSS CVDD CVDD DVDD VSS HD2 AFSX1 DVDD HD1 AXR0 8 AXR1 7 ED22 ED21 ED23 GP0 6 EXT_INT6 CLKS1 SCL1 VSS GP0 7 EXT_INT7 VSS VSS ED13 GP1 13 ED15 GP1 15 ED14 GP1 14 VSS VSS HDS1 AXR0 9 AXR1 6 HAS ACLKX1 HD0 AXR0 11 AXR1 4 ED24 ED25 DVDD CVDD DVDD ...

Page 47: ...X0 TOUT1 AXR0 4 AXR1 11 CLKX0 ACLKX0 TINP0 AXR0 3 AXR1 12 TOUT0 AXR0 2 AXR1 13 CLKR0 ACLKR0 DX0 AXR0 1 AXR1 14 FSX0 AFSX0 FSR0 AFSR0 DR0 AXR0 0 AXR1 15 CLKS0 AHCLKR0 FSX1 DX1 AXR0 5 AXR1 10 CLKX1 AMUTE0 CLKR1 AXR0 6 AXR1 9 DR1 SDA1 FSR1 AXR0 7 AXR1 8 SCL0 SDA0 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122...

Page 48: ...and DA601 Digital Signal Processors In addition to fixed point instructions these functional units execute floating point instructions Enhanced DMA Controller 16 channel L2 Cache Memory 4 Banks 64K Bytes Total 4 Way Clock Generator Oscillator and PLL x4 through x25 Multipliers 1 through 32 Dividers L2 Memory DA610 192K Bytes DA601 64K Bytes R2 ROM 512K Bytes Total EMIF32 McASP1 McASP0 McBSP1 McBSP...

Page 49: ...ction architecture executes 70 of Instructions in 1 or 2 system clocks 48 MIPS and 25 MIPS versions available Expanded interrupt handler Memory 4352 or 2304 Bytes RAM 64 or 32 kB Flash In system programmable in 512 byte sectors Digital Peripherals 40 25 Port I O All 5 V tolerant with high sink current Hardware enhanced SPI SMBus and one or two enhanced UART serial ports Four general purpose 16 bit...

Page 50: ...ant With on chip Power On Reset VDD monitor Voltage Regulator Watchdog Timer and clock oscillator C8051F340 1 2 3 4 5 6 7 8 9 A B devices are truly stand alone System on a Chip solutions The Flash memory can be reprogrammed in circuit providing non volatile data storage and also allowing field upgrades of the 8051 firmware User software has complete control of all peripherals and may individually ...

Page 51: ...0 3 XTAL2 P0 4 P0 5 P0 6 CNVSTR P0 7 VREF Port 1 Drivers Port 2 Drivers Port 3 Drivers P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 P2 0 P2 1 P2 2 P2 3 P2 4 P2 5 P2 6 P2 7 P3 0 C2D Supply Monitor System Clock Setup External Oscillator Internal Oscillator XTAL1 XTAL2 Low Freq Oscillator Clock Multiplier Clock Recovery USB Peripheral Controller 1 kB RAM Full Low Speed Transceiver SFR Bus Voltage Regulato...

Page 52: ...for the C2 Debug Interface P3 0 C2D 10 D I O D I O Port 3 0 See Section 15 for a complete description of Port 3 Bi directional data signal for the C2 Debug Interface REGIN 11 7 Power In 5 V Regulator Input This pin is the input to the on chip volt age regulator VBUS 12 8 D In VBUS Sense Input This pin should be connected to the VBUS signal of a USB network A 5 V signal on this pin indi cates a USB...

Page 53: ... In Port 2 0 See Section 15 for a complete description of Port 2 P2 1 37 17 D I O or A In Port 2 1 P2 2 36 16 D I O or A In Port 2 2 P2 3 35 15 D I O or A In Port 2 3 P2 4 34 14 D I O or A In Port 2 4 P2 5 33 13 D I O or A In Port 2 5 P2 6 32 12 D I O or A In Port 2 6 P2 7 31 11 D I O or A In Port 2 7 P3 0 30 D I O or A In Port 3 0 See Section 15 for a complete description of Port 3 P3 1 29 D I O ...

Page 54: ... Port 4 0 See Section 15 for a complete description of Port 4 P4 1 21 D I O or A In Port 4 1 P4 2 20 D I O or A In Port 4 2 P4 3 19 D I O or A In Port 4 3 P4 4 18 D I O or A In Port 4 4 P4 5 17 D I O or A In Port 4 5 P4 6 16 D I O or A In Port 4 6 P4 7 15 D I O or A In Port 4 7 Table 4 1 Pin Definitions for the C8051F340 1 2 3 4 5 6 7 8 9 A B Continued Name Pin Numbers Type Description 48 pin 32 p...

Page 55: ...47 46 45 44 43 42 41 40 39 38 37 VBUS P2 2 P2 0 P1 7 P1 6 P1 2 P2 4 P2 3 P3 5 P3 4 P3 2 P3 1 P2 1 P0 6 P3 3 P0 7 P0 2 D REGIN P0 3 P3 0 P1 4 P1 5 P0 5 P1 1 P1 0 P0 4 P1 3 13 14 15 16 17 18 19 20 21 22 23 24 P2 6 P2 5 C8051F340 1 4 5 8 GQ Top View GND D P0 1 P0 0 VDD P2 7 P3 6 P4 1 P4 0 P3 7 P4 2 P4 5 P4 4 P4 3 P4 6 RST C2CK C2D P4 7 MS 8 54 ...

Page 56: ...ock configurations available 100 000 erase cycle typical per sector 20 year typical data retention Performance Characteristics High performance 90 ns access time 0 7 s typical sector erase time Low power consumption typical values at 5 MHz 400 nA standby mode current 15 mA read current 40 mA program erase current 400 nA Automatic Sleep mode current Package options 48 ball Fine pitch BGA 64 ball Fo...

Page 57: ...ll Voltage Range VCC 2 7 3 6 V 90 100 Max access time ns 90 100 Max CE access time ns 90 100 Max OE access time ns 25 25 Input Output Buffers X Decoder Y Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator Timer VCC Detector State Control Command Register VCC VSS WE BYTE CE OE STB STB DQ15 DQ0 A 1 Sector Switches RY BY RESET Data Latch Y Gating Cell Matrix Address...

Page 58: ...28 27 26 Standard TSOP Pin Configuration A19 A0 20 addresses DQ14 DQ0 15 data inputs outputs DQ15 A 1 DQ15 data input output word mode A 1 LSB address input byte mode BYTE Selects 8 bit or 16 bit mode CE Chip enable OE Output enable WE Write enable RESET Hardware reset pin RY BY Ready Busy output VCC 3 0 volt only single power supply see Product Selector Guide for speed options and voltage supply ...

Page 59: ...7 16 15 14 NC IN NC IN NC TL071 FK PACKAGE TOP VIEW NC OFFSET N1 NC NC NC NC NC OFFSET N2 NC CC V TL072 FK PACKAGE 3 2 1 20 19 9 10 11 12 13 4 5 6 7 8 18 17 16 15 14 4IN NC VCC NC 3IN TL074 FK PACKAGE TOP VIEW 1IN 1OUT NC 3IN 4IN 2IN NC 3OUT 4OUT 2OUT 1 2 3 4 8 7 6 5 OFFSET N1 IN IN VCC NC VCC OUT OFFSET N2 TL071 TL071A TL071B D P OR PS PACKAGE TOP VIEW 1 2 3 4 8 7 6 5 1OUT 1IN 1IN VCC VCC 2OUT 2I...

Page 60: ... 4 V Power On Reset Generator With a Delay Time Thereafter the supervisory circuit monitors VDD and of 130 ms keeps the RESET output active as long as VDD Push Pull or Open Drain RESET Outputs remains below the threshold voltage VIT An internal timer delays the return of the output to the inactive SOT23 6 Package state to ensure proper system reset The delay time Package Temperature Range 40 C to ...

Page 61: ... Logic and Timer VIT 0 551 V VDD MR PFI GND RESET PFO TPS3103 _ _ Reset Logic and Timer 0 551 V VDD MR SENSE GND RSTVDD Reset Logic and Timer RSTSENSE TPS3106 VIT TPS3103xxx TPS3106xxx TPS3110xxx SLVS363E AUGUST 2001 REVISED SEPTEMBER 2007 MS 8 60 ...

Page 62: ...R V PFI 0 551 V VDD VIT RESET PFO L 0 X 1 L L L 1 X L H H 0 0 L L H 0 1 H L H 1 0 L H H 1 1 H H 1 X Don t care Table 2 TPS3106 FUNCTION TABLE MR V SENSE 0 551 V VDD VIT RSTVDD RSTSENSE L X 1 X L L H 0 0 L L H 0 1 H L H 1 0 L H H 1 1 H H 1 X Don t care Table 3 TPS3110 FUNCTION TABLE 1 MR V SENSE 0 551 V VDD VIT RESET L X 2 X L H 0 0 L H 0 1 L H 1 0 L H 1 1 H 1 Function of watchdog timer not shown 2...

Page 63: ...nnect to VDD if not used PFO TPS3103 5 Power fail output Goes high when voltage at PFI rises above 0 551 V TPS3103 RESET 1 Active low reset output Either push pull or open drain output stage TPS3110 Active low reset output Logic level at RSTSENSE only depends on the voltage at SENSE and RSTSENSE TPS3106 5 the status of MR Active low reset output Logic level at RSTVDD only depends on the voltage at...

Page 64: ...U04 devices contain six independent inverters They perform the Boolean function Y A in positive logic ORDERING INFORMATION TA PACKAGE ORDERABLE PART NUMBER TOP SIDE MARKING PDIP N Tube of 25 SN74HCU04N SN74HCU04N Tube of 50 SN74HCU04D SOIC D Reel of 2500 SN74HCU04DR HCU04 SOIC D Reel of 250 SN74HCU04DT HCU04 40 C to 85 C SOP NS Reel of 2000 SN74HCU04NSR HCU04 40 C to 85 C SSOP DB Reel of 2000 SN74...

Page 65: ...yond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTES 1 The input and output voltage ratings may be exceeded if the input and output current ratings are observed 2 The package thermal impedance is calculated in accordance with JESD 51 7 recommended operating conditions see No...

Page 66: ...he TDA7563B is a new BCD technology quad bridge type of car radio amplifier in Flexiwatt27 package specially intended for car radio applications Thanks to the DMOS output stage the TDA7563B has a very low distortion allowing a clear powerful sound Among the features its superior efficiency performance coming from the internal exclusive structure makes it the most suitable device to simplify the th...

Page 67: ...OUT LF OUT LR OUT LR Short Circuit Protection Diagnostic Short Circuit Protection Diagnostic Short Circuit Protection Diagnostic 16 30dB Reference CLK DATA SVR AC_GND TAB S_GND PW_GND F F R R RF RR LF LR ST BY MUTE 16 30dB 16 30dB 16 30dB IN RF C1 0 22μF IN RR C2 0 22μF OUT RF OUT RR IN LF C3 0 22μF IN LR C4 0 22μF OUT LF OUT LR D00AU1231A C5 1μF C6 10μF TAB 47K Vcc1 Vcc2 C8 0 1μF V 4V VCC C7 3300...

Page 68: ... 18 19 20 25 26 22 21 23 24 27 D00AU1416 TAB STBY PW_GND LR OUT LR CD OUT OUT LR VCC1 OUT LF PW_GND LF OUT LF SVR IN LF IN LR S_GND IN RR IN RF AC GND OUT RF PW_GND RF OUT RF VCC2 CK OUT RR OUT RR PW_GND RR DATA TAB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 25 26 22 21 23 24 27 Flexiwatt27 vertical Flexiwatt27 horizontal CD N C N C OUT2 PWGND OUT4 N C N C CK OUT3 N C N C OUT3 PWGND PWGND ...

Page 69: ...s where space saving is critical the SOT23 package 2 8 x 2 9mm or the DFN package 3 x 3mm simplify the board design because they can be placed everywhere TS971ILT SOT23 5L 1 2 3 4 5 Inverting input Non inverting input Output VDD VCC TS971ID TS971IDT SO 8 1 2 3 4 5 6 7 8 Inverting Input 1 N C Non inverting Input 1 VDD VCC Output 2 N C N C 1 2 3 4 5 6 7 8 Inverting Input 1 Output 1 Non inverting Inp...

Page 70: ... are very high efficiencies up to 90 are easy to achieve External shutdown is included featuring an ultra low stand by current of 30nA The LM2734 utilizes current mode control and in ternal compensation to provide high performance regulation over a wide range of operating conditions Additional fea tures include internal soft start circuitry to reduce inrush current pulse by pulse current limit the...

Page 71: ...ion 1 BOOST Boost voltage that drives the internal NMOS control switch A bootstrap capacitor is connected between the BOOST and SW pins 2 GND Signal and Power ground pin Place the bottom resistor of the feedback network as close as possible to this pin for accurate regulation 3 FB Feedback pin Connect FB to the external resistor divider to set output voltage 4 EN Enable control input Logic high en...

Page 72: ...ce to Clock Jitter Single Ended Output Buffer with 2nd order Analog LPF Digital De emphasis for 32 44 1 48kHz sampling Zero Detect function Channel Independent Digital Attenuator Linear 256 steps 3 wire Serial and I2 C Bus P I F for mode setting I F format MSB justified LSB justified 16bit 20bit 24bit I 2 S TDM Master clock 256fs 384fs 512fs or 768fs or 1152fs Normal Speed Mode 128fs 192fs 256fs o...

Page 73: ...Layout 6 5 4 3 2 1 MCLK BICK LRCK SDTI1 RSTB SMUTE CSN CAD0 7 DIF0 CDTI SDA 8 DZF1 DZF2 AVDD AVSS VCOM LOUT1 ROUT1 P S AK4359 Top View 10 9 SDTI2 SDTI3 SDTI4 11 DIF1 12 LOUT2 ROUT2 LOUT3 ROUT3 25 26 27 28 29 30 24 23 21 22 20 19 ACKS CCLK SCL DEM0 13 DVDD 14 LOUT4 ROUT4 18 17 DVSS 15 DEM1 I2C 16 MS 8 72 ...

Page 74: ...dio Serial Data Input Pin 11 SDTI4 I DAC4 Audio Serial Data Input Pin 12 DIF1 I Audio Data Interface Format Pin 13 DEM0 I De emphasis Filter Enable Pin 14 DVDD Digital Power Supply Pin 4 5 5 5V 15 DVSS Digital Ground Pin I2C I Control Mode Select Pin in serial mode L 3 wire Serial H I2 C Bus 16 DEM1 I De emphasis Filter Enable Pin in parallel mode 17 ROUT4 O DAC4 Rch Analog Output Pin 18 LOUT4 O D...

Page 75: ...l analog multiplexers or demultiplexers with common select logic Each multiplexer has four independent inputs outputs pins nY0 to nY3 and a common input output pin nZ The common channel select logics include two digital select inputs pins S0 and S1 and an active LOW enable input pin E When pin E LOW one of the four switches is selected low impedance ON state with pins S0 and S1 When pin E HIGH all...

Page 76: ...12 1Y0 independent input or output 13 1Z common input or output 14 1Y1 independent input or output 15 1Y2 independent input or output 16 VCC positive supply voltage handbook halfpage 4052 MNB039 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 2Y0 2Y2 2Z 2Y3 2Y1 E VEE GND S1 S0 1Y3 1Y0 1Z 1Y1 1Y2 VCC Fig 1 Pin configuration DIP16 SO16 and T SSOP16 Fig 2 Pin configuration DHVQFN16 1 The die substrate is atta...

Page 77: ... S0 S1 E 2Z 2Y3 2Y2 2Y1 2Y0 1Y3 1Y2 1Y1 1Y0 10 Fig 3 Logic symbol handbook halfpage MNB041 11 15 14 12 4 2 5 9 1 10 0 6 G4 MDX 0 3 4 1 3 2 1 0 13 3 Fig 4 IEC logic symbol handbook full pagewidth MNB042 1 OF 4 DECODER LOGIC LEVEL CONVERSION 7 8 VEE GND VCC 12 13 16 3 14 15 11 10 9 6 S0 S1 E 1 5 2 1Y0 1Z 2Z 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 4 Fig 5 Functional diagram MS 8 76 ...

Page 78: ...ady DC levels the cur rent sources decrease to 275µA to improve negative slew rate and improve low state noise margins An auto detect standby mode reduces supply current if both SCL and SDA are high The LTC1694 is available in a 5 pin SOT 23 package requiring virtually the same space as two surface mount resistors Notebook and Palmtop Computers Portable Instruments Battery Chargers Industrial Cont...

Page 79: ...RES Slew Rate Detector Threshold SMBus VTHRES 0 2 0 5 V µs tr SMBus Rise Time Bus Capacitance 200pF Note 2 0 32 1 0 µs Standard Mode I2C Bus Rise Time Bus Capacitance 400pF Note 3 0 30 1 0 µs fMAX SMBus Maximum Operating Frequency Note 4 100 kHz Note 1 Absolute Maximum Ratings are those values beyond which the life of a device may be impaired Note 2 The rise time of an SMBus line is calculated fro...

Page 80: ...40 0 35 0 30 0 25 0 20 0 15 0 10 0 05 0 0 50 75 1694 G05 25 25 100 125 VCC 6V VCC 2 7V VCC 5V Slew Rate Detector Threshold Standby Mode Supply Current TEMPERATURE C 50 SUPPLY CURRENT µA 100 1694 G06 0 50 100 90 80 70 60 50 40 30 20 25 25 75 125 VCC 6V VCC 2 7V VCC 5V Pull Up Current at SMBus 0V Boosted Pull Up Current SMBus VOLTAGE V 0 3 5 3 0 2 5 2 0 1 5 1 0 0 5 0 3 5 LT1694 G03 1 2 4 6 7 BOOSTED...

Page 81: ...L ONE 1694 BD 1 175µA 100µA VCC 5 SMBus1 SMBus2 2 GND 4 BLOCK DIAGRA W Figure 1 LTC1694 VCC GND VCC 5V C1 0 1µF SMBus1 SMBus2 5 4 1 2 HP5082 2080 TEST RAMP VOLTAGE BSS284 VR 1k 10V 1694 f01a LT1360 BOOSTED PULL UP 2 2mA TYP 275µA TYP TEST RAMP VOLTAGE 0µA VCC 1694 F01b 0 5V µs 0V VTHRES IPULL UP VR 1kΩ TEST CIRCUITS MS 8 80 ...

Page 82: ... limit protection for regulators 1 2 3 and 4 Delayed second current limit protection for the power switch at short circuit The regulator outputs and the power switch are DC short circuit safe to ground and supply VP GENERAL DESCRIPTION The TDA3681 is a multiple output voltage regulator with a power switch and an ignition buffer It is intended for use in car radios with or without a microcontroller...

Page 83: ...TOR 4 REGULATOR 1 16 14 7 TEMPERATURE LOAD DUMP PROTECTION 17 11 9 3 10 8 13 POWER SWITCH BACKUP SWITCH BACKUP CONTROL OR GND 14 4 V TDA3681J TDA3681JR RES REG2 REG4 REG1 14 V 3 A 14 V 100 mA 5 V 300 mA 3 3 V 1 A 8 5 V 600 mA SW VP1 ENSW EN4 VP2 EN1 3 CRES BU HOLD 12 1 IGNITION BUFFER 5 IGNOUT IGNIN 6 4 REGULATOR 3 REG3 5 V 1400 mA 2 15 Fig 1 Block diagram of TDA3681J and TDA3681JR MS 8 82 ...

Page 84: ...ULATOR 1 16 13 4 TEMPERATURE LOAD DUMP PROTECTION 14 8 6 20 7 5 10 POWER SWITCH BACKUP SWITCH BACKUP CONTROL OR GND 14 4 V TDA3681TH RES REG2 REG4 REG1 14 V 3 A 14 V 100 mA 5 V 300 mA 3 3 V 1 A 8 5 V 600 mA SW VP1 ENSW EN4 11 HEATTAB n c n c 15 18 VP2 EN1 3 CRES BU HOLD 9 17 IGNITION BUFFER 2 IGNOUT IGNIN 3 1 REGULATOR 3 REG3 5 V 1400 mA 19 12 Fig 2 Block diagram of TDA3681TH MS 8 83 ...

Page 85: ...reset delay capacitor EN4 9 enable input for regulator 4 EN1 3 10 enable input for regulators 1 and 3 ENSW 11 enable input for power switch HOLD 12 hold output active LOW GND 13 ground BU 14 backup switch output REG2 15 regulator 2 output SW 16 power switch output VP1 17 supply voltage heat tab heat tab it is strongly recommended to connect the heat tab to ground handbook halfpage TDA3681J TDA3681...

Page 86: ...t for regulator 4 EN1 3 7 enable input for regulators 1 and 3 ENSW 8 enable input for power switch HOLD 9 hold output active LOW GND 10 ground HEATTAB 11 heat tab connection note 1 REG2 12 regulator 2 output BU 13 backup switch output VP1 14 supply voltage n c 15 not connected SW 16 power switch output REG1 17 regulator 1 output n c 18 not connected REG3 19 regulator 3 output VP2 20 second supply ...

Page 87: ... Linear Phase Digital Anti Alias Filtering Single ended Input Digital HPF for DC Offset cancel S N D 92dB DR 102dB S N 102dB Sampling Rate Ranging from 8kHz to 96kHz Master Clock 256fs 384fs 512fs 768fs 8kHz 48kHz 256fs 384fs 48kHz 96kHz Input level TTL CMOS Master Slave Mode Audio Interface 24bit MSB justified I 2 S selectable Power Supply 4 5 5 5V Analog 2 7 5 5V Digital Ta 20 85 C Small 16pin T...

Page 88: ...6kHz 8kHz to 96kHz 8kHz to 96kHz 4kHz to 96kHz 8kHz to 216kHz S N D 88dB 92dB 92dB 96dB 94dB DR 102dB 102dB 102dB 106dB 102dB VIH TTL Level Mode 2 2V 2 2V 2 2V 2 4V Not Available VA Analog Supply 2 7 to 5 5V 4 5 to 5 5V 4 5 to 5 5V 4 5 to 5 5V 4 5 to 5 5V 2 7 to 5 5V VD Digital Supply 2 7 to 5 5V 2 7 to 3 6V 2 7 to 5 5V 3 0 to 5 5V 96kHz 3 0 to 5 5V HPF Disable Available Not Available Not Availabl...

Page 89: ...Mode at Power down mode 11 MCLK I Master Clock Input Pin 12 SCLK I O Audio Serial Data Clock Pin L Output in Master Mode at Power down mode 13 PDN I Power Down Mode Reset Pin H Power up L Power down Reset The AK5358A must be reset once upon power up 14 DIF I Audio Interface Format Pin H 24bit I2 S Compatible L 24bit MSB justified 15 CKS2 I Mode Select 2 Pin 16 CKS0 I Mode Select 0 Pin Note All inp...

Page 90: ...at least 1 5 V more positive than the input common mode voltage The low supply current drain is independent of the magnitude of the supply voltage Applications include transducer amplifiers dc amplification blocks and all the conventional operational amplifier circuits that now can be more easily implemented in single supply voltage systems For example the LM124 can be operated directly from the s...

Page 91: ...r line driver with 3 state outputs The 3 state outputs are controlled by the output enable inputs 1OE and 2OE A HIGH on nOE causes the outputs to assume a high impedance OFF state Schmitt trigger action at all inputs makes the circuit highly tolerant for slower input rise and fall times The 74LVC2244A is designed with 30 Ω series termination resistors in both HIGH and LOW output stages to reduce l...

Page 92: ...Y0 1A1 2Y1 1A2 2Y2 1A3 2Y3 GND VCC 2OE 1Y0 2A0 2A1 1Y2 1Y1 2A2 1Y3 2A3 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 2244 MNA357 handbook halfpage 1A3 1A2 1A1 1A0 2 4 6 8 1 1Y0 1Y1 18 16 14 12 1Y2 1Y3 1OE MNA360 2A3 2A2 2A1 2A0 17 15 13 11 19 2Y0 2Y1 3 5 7 9 2Y2 2Y3 2OE Fig 2 Functional diagram Fig 3 IEC logic symbol handbook halfpage 12 14 2 4 6 8 18 16 1 EN MNA359 9 7 17 15 13 11 3 5 19 EN ...

Page 93: ...MS 8 92 ...

Page 94: ... 13 G1 TINP0 AXR0 3 AXR1 12 G2 TOUT1 AXR0 4 AXR1 11 F1 DX1 AXR0 5 AXR1 10 L2 CLKR1 AXRO 6 AXR1 9 M1 FSR1 AXR0 7 AXR1 8 M3 HD1 AXR0 8 AXR1 7 D20 HDS1 AXR0 9 AXR1 6 E19 HDS2 AXR0 10 AXR1 5 F18 HD0 AXR0 11 AXR1 4 E20 HCNTL0 AXR0 12 AXR1 3 G18 HCS AXR0 13 AXR1 2 F20 HCNTL1 AXR0 14 AXR1 1 G19 HR W AXR0 15 AXR1 0 G20 RESET A13 ECLKIN Y11 CLKMODE0 C4 CLKOUT3 D10 CLKIN A3 TDI A7 TDO A8 TCK A6 TMS B7 TRST ...

Page 95: ...ND E4 GND E17 GND F19 GND G4 GND G17 GND H4 GND H17 GND J4 GND J9 GND J10 GND J11 GND J12 GND K2 GND K9 GND K10 GND K11 GND K12 GND K20 GND L9 GND L10 GND L11 GND L12 GND M4 GND M9 GND M10 GND M11 GND M12 GND M17 GND N4 GND N17 GND P4 GND P17 GND P19 GND T4 GND T17 GND U4 GND U8 GND U9 GND U13 GND U17 GND U20 GND W1 GND W5 GND W11 GND W16 GND W20 GND Y1 GND Y2 GND Y13 GND Y19 GND Y20 U21C TMS320DA...

Page 96: ...4 GND 8 KEY 6 GND 10 GND 12 TRST 2 TMS 1 TCK_RET 9 TCK 11 TDI 3 TDO 7 EMU0 13 EMU1 14 J9 TSW 107 07 L D 006 DNP 3P3V DGND DGND 3P3V DGND 3P3V 3P3V DGND DGND AGND 3P3V JTAG_TRST DSP_TXD DSP_RXD JTAG_TMS JTAG_TCK JTAG_TDI JTAG_EMU0 JTAG_EMU1 JTAG_TDO JTAG Debug Programming Circuit for DA610 3 Pin header for RS232 Comm DNP for Production R274 4 7K R273 4 7K R290 4 7K R280 4 7K R287 4 7K R291 4 7K R28...

Page 97: ...56 CLK 68 DQ10 77 A3 60 A4 61 A5 62 A6 63 A7 64 A8 65 A9 66 DQ8 74 DQ9 76 DQ11 79 DQ12 80 DQ13 82 DQ14 83 DQ15 85 DQ16 31 DQ17 33 DQ18 34 DQ19 36 DQ20 37 DQ21 39 DQ22 40 DQ23 42 GND 44 GND 58 GND 72 GND 86 VSSQ 12 VSSQ 6 VSSQ 32 VSSQ 38 VSSQ 46 VSSQ 52 VSSQ 78 VSSQ 84 VDD 1 VDD 15 VDD 29 VDD 43 VDDQ 3 VDDQ 9 VDDQ 35 VDDQ 41 VDDQ 49 VDDQ 55 VDDQ 75 VDDQ 81 CAS 18 CKE 67 RAS 19 WE 17 CS 20 DQM0 16 D...

Page 98: ...E LED DGND DGND DGND 5V_ON DGND 3P3V_ON 5V_ON DGND 3P3V_ON DGND DGND DGND DGND 3P3V_ON DGND DGND USB_D USB_D VBUS I2C_SDA I2C_SCL DAC_MUTE MUX0 DAC_RESET ADC_PDN MUX1 RESET REM_IN_TTL LOWVOLT AUD_SENSE I2C_SCL2 I2C_SDA2 MICDETECT DSP_GP1 DSPLY_PWR_EN DSPRESET POW_EN MUTE C2 Interface forDebug andProgramming ofMicrocontroller VTEMP canbe amaximum of2 4V The microcontroller internally regulates the ...

Page 99: ...GND POW_EN RESET DSPLY_PWR_EN REM_IN_TTL LOWVOLT POW_EN F1 plugs into socket SENSE has0 551Vthreshold Coilcraft MSS7341 153MLB TDK C3216X5R1C106M Place Feedback line away from inductor preferably on other side of the board PlaceL22 D22 C278close together Place C144 C428 close to VIN pin Make VIN SW and GND lines as thick and as short as possible The 1P2V supply may have tosource as much as 1A The ...

Page 100: ...T C146 10uF 10 11 U16E 74HCU04 C300 0 1uF C210 0 1uF R320 33 R321 33 C227 10uF C222 10uF TSSOP16 AINR 1 AINL 2 CKS1 3 VCOM 4 AGND 5 VA 6 VD 7 DGND 8 SDTO 9 LRCK 10 MCLK 11 SCLK 12 PDN 13 DIF 14 CKS2 15 CKS0 16 U6 AK5358ET AGND AGND AGND AGND AGND AGND 3P3V 3P3V 3P3V 3P3V 3P3V AGND AGND AGND AGND AGND 3P3V 3P3V AGND AGND DGND 3P3V DGND 5V AGND 5VA 5VA 5VA 5VA 3P3V DGND 3P3V DGND DGND 3P3V I2S_IN 3 ...

Page 101: ...23 ROUT1 24 LOUT1 25 VCOM 26 AVSS 27 AVDD 28 DZF2 29 DZF1 30 U9 AK4359VF GND2 AGND 5V_ON 5V_ON 5V_ON DAC_MCLK M_BCLK DAC_RESET DAC_MUTE I2S_OUT 3 0 LOUT1 LOUT2 LOUT3 LOUT4 ROUT1 ROUT2 ROUT3 ROUT4 M_LRCLK MCLK 24 576 MHz BCLK 3 072 MHz LRCLK 48 kHz CH1 CH5 CH2 CH6 CH3 CH7 CH4 CH8 DW GNO PART NO PART NAME PRODUCT MODE SCALE 1 1 UNIT MM SIZE REV DRAWN BY CHECKED BY APPROVED BY DATA DATA DATA DESCRIPT...

Page 102: ...100 C85 10uF 8P5VA 8P5VA AGND AGND AGND AGND 8P5VA 8P5VA AGND 4P25V 4P25V AGND AGND 8P5VA AGND 4P25V AGND AGND MicL_analog MicR_analog MICDETECT 13 4dB 0 9dB 1 5mA 2 34KHz Mic In_L 13 4dB 0 9dB 1 5mA 2 34KHz Mic In_R DW GNO PART NO PART NAME PRODUCT MODE SCALE 1 1 UNIT MM SIZE REV DRAWN BY CHECKED BY APPROVED BY DATA DATA DATA DESCRIPTON DATA APPROVED DESCRIPTON REV REV Place Place DATA EVR Microp...

Page 103: ...48 240 C397 47pF C398 0 22uF 1206 SX28 0603ESDA 3 1 2 D27 BAV70 SOT R328 1k AGND AGND 12V AGND VCAR AGND VCAR AGND AGND AGND 12V 12V AGND AGND AGND AGND AUX_R AUX_L AUXR AUXR AUXL AUXL AL AL AR AR Line level Input 1 0Vrms 2 8Vp p DW GNO PART NO PART NAME PRODUCT MODE SCALE 1 1 UNIT MM SIZE REV DRAWN BY CHECKED BY APPROVED BY DATA DATA DATA DESCRIPTON DATA APPROVED DESCRIPTON REV REV Place Place DA...

Page 104: ... 1 C79 47pF R336 240 R20 56 2k R63 3 3k R57 10 0k 1 SX25 0603ESDA C44 0 22uF 1206 1 TP25 TEST POINT SX11 0603ESDA R21 56 2k R69 10 0k 1 R385 1k R18 56 2k R342 1k R350 1k C81 47pF R62 10 0k 1 SX9 0603ESDA 3 1 2 D18 BAW56 SOT SX35 0603ESDA AGND 12V AGND 12V VCAR AGND VCAR AGND VCAR AGND VCAR AGND AGND AGND AGND AGND 12V 12V 12V 12V AGND AGND AGND AGND R4 spkr_lin1 spkr_lin2 spkr_lin1 spkr_lin2 spkr_...

Page 105: ...388 1k R359 1k 6 5 J2C RCA JACK OCTAL R360 1k R17 56 2k R371 1k R11 56 2k R362 1k C55 0 22uF 1206 R372 1k R13 56 2k R395 1k SX32 0603ESDA AGND 12V AGND 12V AGND VCAR AGND AGND AGND VCAR AGND VCAR AGND AGND AGND VCAR AGND AGND AGND AGND 12V 12V 12V 12V spkr_rin2 spkr_rin2 spkr_lin2 spkr_lin2 spkr_lin1 spkr_rin1 spkr_lin1 spkr_rin1 R2 R2 L2 L2 L1 L1 R1 R1 RIN2 LIN2 LIN1 RIN1 CH3 CH4 CH7 CH8 DW GNO P...

Page 106: ...R254 20k R305 475k R304 475k R172 475k R93 475k 1 2 D19 1N4148W C380 10uF R162 2 8M R106 475k AGND 7VB 5VB AGND AGND AGND 7VB 5VB 5V_ON AGND AGND VCAR AGND 5V_ON AGND 3P3V_ON VCAR AUD_SENSE L1 R1 L2 L3 L4 R2 R3 R4 AL AR AL AR L1 R1 L2 L3 L4 R2 R3 R4 DW GNO PART NO PART NAME PRODUCT MODE SCALE 1 1 UNIT MM SIZE REV DRAWN BY CHECKED BY APPROVED BY DATA DATA DATA DESCRIPTON DATA APPROVED DESCRIPTON RE...

Page 107: ...J7C RCA JACK OCTAL R245 2 2k C291 820pF R191 100 C268 100pF R231 100k R228 1 5k Q24 2SD2114K Q22 2SD2114K C389 100pF R242 2 4k C264 100pF C272 100pF C246 22uF 16V Q23 2SD2114K R195 100 5 6 OUT 7 U20B TS974IPT C387 100pF C242 22uF 16V R227 1 8k 14 13 J7G RCA JACK OCTAL C271 820pF GND2 GND2 GND2 GND2 GND2 GND2 GND2 GND2 GND2 GND2 GND2 GND2 GND2 8P5VA 4P25V 4P25V 4P25V 4P25V 4P25V 4P25V 4P25V 4P25V G...

Page 108: ...26 2SD2114K R236 2 4k R225 1 5k R247 2 2k C262 100pF 16 15 J7H RCA JACK OCTAL C400 100pF R213 1 5k R377 4 3k C257 820pF C269 820pF R218 1 8k C293 820pF R207 1 5k R380 4 3k R226 10k R224 1 8k Q25 2SD2114K C243 22uF 16V R212 1 8k R401 100 R262 20k GND2 GND2 GND2 GND2 GND2 GND2 GND2 GND2 GND2 GND2 GND2 GND2 4P25V 4P25V 4P25V 4P25V GND2 8P5VA 4P25V 4P25V 4P25V 4P25V GND2 GND2 GND2 GND2 GND2 GND2 GND2 ...

Page 109: ...1 6 4 Place protectiondiode as close tothe connector aspossible I2C Display Module Connector USB Connector AUX Connector TOP VIEW Place protectiondiode as close tothe connector aspossible Red White DW GNO PART NO PART NAME PRODUCT MODE SCALE 1 1 UNIT MM SIZE REV DRAWN BY CHECKED BY APPROVED BY DATA DATA DATA DESCRIPTON DATA APPROVED DESCRIPTON REV REV Place Place DATA EVR I O Connectors MS 8 MAIN ...

Page 110: ...c1 7 CLK 23 DATA 26 PGND1 19 OUT2 22 OUT2 24 PGND2 25 OUT3 10 OUT3 8 PGND3 9 OUT4 6 OUT4 4 PGND4 3 U17 TDA7563B R94 2 67k 1 R186 10 0k 1 C91 0 47uF 25V X7R C240 1nF R184 698 1 R88 2 67k 1 R177 2 67k 1 Q29 MMBT3904 C88 0 47uF 25V X7R R52 698 1 C115 1nF 1 2 L21 1nH C251 1nF C368 1nF C363 1nF C29 0 1uF R70 10 0k 1 C224 0 47uF 25V X7R R37 10k C94 0 47uF 25V X7R R185 2 67k 1 R199 10 0k 1 C367 1nF C26 4...

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