Rev. 1.3
21
C8051F340/1/2/3/4/5/6/7/8/9/A/B
Figure 1.2. C8051F342/3/6/7 Block Diagram
Analog Peripherals
10-bit
200 ksps
ADC
A
M
U
X
Temp
Sensor
2 Comparators
+
-
VREF
VDD
CP0
VDD
+
-
CP1
VREF
Debug / Programming
Hardware
Port 0
Drivers
P0.0
AIN0 - AIN20
Port I/O Configuration
Digital Peripherals
Priority
Crossbar
Decoder
Crossbar Control
Power-On
Reset
Power
Net
UART0
Timers 0, 1,
2, 3
PCA/WDT
SMBus
SPI
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4
P0.5
P0.6/CNVSTR
P0.7/VREF
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
Supply
Monitor
System Clock Setup
External
Oscillator
Internal
Oscillator
XTAL1
XTAL2
Low Freq.
Oscillator*
Clock
Multiplier
Clock
Recovery
USB Peripheral
Controller
1 kB RAM
Full / Low
Speed
Transceiver
SFR
Bus
Voltage
Regulator
D+
D-
VBUS
VDD
VREG
GND
C2CK/RST
Reset
CIP-51 8051
Controller Core
64/32 kB ISP FLASH
Program Memory
256 Byte RAM
4/2 kB XRAM
C2D
*Low Frequency Oscillator option not available on C8051F346/7
MS-8
50
Summary of Contents for MS-8
Page 3: ...MS 8 PACKAGING LITHIUM COIN BATTERY 3VDC CR2032 MS 8 2 ...
Page 31: ...MS 8 30 Top layer ...
Page 32: ...MS 8 31 Power layer ...
Page 33: ...MS 8 32 Inner l3 layer ...
Page 34: ...MS 8 33 Inner l4 layer ...
Page 35: ...MS 8 34 Bottom layer ...
Page 36: ...MS 8 35 ...
Page 37: ...MS 8 36 ...
Page 93: ...MS 8 92 ...