8 - 1
8.
Circuit Description
8.1
Transmitter Section
8.1.1 PLL Circuit (CMB-257)
The unit obtains the required frequency using the PLL type frequency
synthesizer. In short, the self-excited oscillator using L and C is
controlled using a stable crystal oscillator frequency to generate an
equivalent stable self-excited oscillator frequency. For details, see the
block diagram in Fig. 8.1 below.
DC control voltage for frequency control, which is supplied by the PLL
circuit, is applied to the variable capacity diodes, which is in the VCO.
This DC control voltage varies the value of C in the LC circuit to control
the oscillation frequency. An oscillator output passing through the buffer
amplifier TR4 is fed back to the PLL circuit, and another oscillator output
passing through the other buffer amplifier TR6 is supplied to the
transmission oscillator. This output is approxi26dBm.
8.1.2 Lock Sensor (CMB-257)
The purpose of the lock sensor is to inhibit transmission when the
transmitting PLL circuit is unlocked. This prevents transmission of an
undesirable frequency. Pin 8 of IC6, which serves as a lock sensor pin,
outputs a narrow pulse of negative logic when PLL is locked, and outputs
a wide pulse of negative logic when PLL is unlocked. When the
transmitter PLL circuit is unlocked, TR7 is turned off, and TR8 is turned
on to reject the signal at the PA section.
8.1.3 Power Amplifier Circuit (CAH-559)
The power amplifier circuit consists of HC1. L3 through L5 and C14
through C19 constitutes a higher harmonic filter, which attenuates
spurious frequencies, including those equivalent to two and three times
the fundamental frequency, etc.
HC1 amp23dBm RF signal from the modulator (CMB-257). HC1
amplifies the RF signal to produce the specified output of +47dBm.
Control
VCO
control
TX channel set
to XMTR
Tx
VCO
L.P.F.
Prescaler
128/129
Phase
Detector
fv
fr
"N"
Counter
Reference
Counter
Synthesizer IC
12.8MHz
uP
Reference
Oscillator
Fig. 8.1 PLL Oscillator
