IWILL VD133, Manual, Page: 56 / 80

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VD133 Pro Series
Chapter 5 BIOS Setup
5.5.1 Bank 0/1 2/3 4/5 DRAM Timing
This item allows you to select the value in this field, depending on whether the board
has paged DRAMs or EDO (extended data output) DRAMs.
Some engineering knowledge is needed prior to handling Auto Configuration.
Options SDRAM 10ns (*) / SDRAM 8ns / Normal / Medium / Fast / Turbo
5.5.2 SDRAM Cycle Length
When synchronous DRAM is installed, the number of clock cycles of CAS latency
depends on the DRAM timing. Do not reset this field from the default value specified
by the system designer.
Options Description
2 2 system clocks
3 (*) 3 system clocks
5.5.3 DRAM Clock
This field allows you to select the DRAM operating frequency to get better performance.
Options Description
Host Clk (*) DRAM clock is the same speed as Front Side Bus
(66/100/133 MHz)
HCLK –33 MHz DRAM clock is set 33 MHz less than the Front Side Bus
HCLK +33 MHz DRAM clock is set 33 MHz greater than the Front Side Bus
5.5.4 DRAM Parity / ECC Check
When enabled, the BIOS will use ECC (Error Checking and Correcting) protocol to
increase integrity of system data. All memory modules used in the system need to
support ECC in order for this function to work properly.
Options Enabled
Disabled (*)
5.5.5 Memory Hole
In order to improve performance, certain space in memory is reserved for ISA cards.
This memory must be mapped into the memory space below 16MB.
Note : This field is for experienced users only.
Options 15M-16M
Disabled (*)