REL1.2
Page 36 of 62
RZ/G1E SODIMM SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Pin
No.
SODIMM Edge Connector
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
174
DU0_DB7(GP2_23)
DU0_DB7/
AC15
O, 3.3V CMOS
DU0 Parallel LCD data 7 (Blue data7).
175
CAN1_RX/MSIOF2_SYNC(G
P1_1)
A17/
K4
I, 3.3V CMOS
Receive input for CAN1 bus (Or) MSIOF2
frame synchronization for transmission.
176
CAN0_RX(GP6_14)
SD1_CD/
AD8
I, 3.3V CMOS
CAN0 Receive
177
CAN1_TX/MSIOF2_SS1(GP
1_2/MDT0)
1
A18/MDT0/
H2
O, 3.3V CMOS/
10K PD
Transmit output for CAN1 bus (Or)
MSIOF2 frame synchronization signal1.
178
CAN0_TX(GP6_15)
SD1_WP/
AE9
O, 3.3V CMOS
CAN0 Transmit
179
GPIO(GP4_24)
SSI_SCK5/
AE22
IO, 3.3V CMOS
General Purpose Input / Output.
180
VIN_3V3
NA
I, 3.3V Power
Supply Voltage.
181
MSIOF2_SS2(GP1_3/MD18
)
1
A19/MD18/
K3
O, 3.3V CMOS/
10K PD
MSIOF2 frame synchronization signal2.
182
GPIO(GP1_14)
EX_CS2#/
D1
I, 3.3V CMOS/
General Purpose Input / Output.
183
VRTC_3V0
NA
I, 3V Power
3V backup coin cell input for RTC.
184
GPIO(GP4_1)
I2C1_SDA/
Y25
IO, 3.3V CMOS/ General Purpose Input / Output.
185
GND
NA
Power
Ground.
186
GND
NA
Power
Ground.
187
POR_B
NA
I, 3.3V CMOS/
10K PD
Active low reset button input.
Important Note: This pin is directly
connected to
RZ/G1E CPU’s PRESET# pin.
Use this pin only for connecting the reset
push button in the carrier board.
188
USB1_DP
USB1_DP/
N24
IO, DIFF
USB1 Host data positive.
189
MSIOF2_SCK(GP1_0)
A16/
J2
O, 3.3V CMOS
MSIOF2 Serial clock for transmission.
Same signal can also work as SCK when a
common clock is used for transmission
and reception.
190
USB1_DM
USB1_DM/
N25
IO, DIFF
USB1 Host data negative.
191
TDO
TDO/
P22
O, 3.3V CMOS
JTAG Test Data Output.
192
VIN_3V3
NA
I, 3.3V Power
Supply Voltage.
193
TRST#
TRST#/
N21
I, 3.3V CMOS
JTAG reset.
194
MSIOF2_TXD(GP0_31/MD
7)
1
A15/
H1
O, 3.3V CMOS/
10K PD
MSIOF2 transmit data.
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