iWave iW-RainboW-G22M, Hardware User'S Manual

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REL1.2
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RZ/G1E SODIMM SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.4 Memory
2.4.1 DDR3 SDRAM
The RZ/G1E SODIMM SOM supports 512MB DDR3 RAM memory by default. This is connected to CPU in 32bit x 1ch
mode where it uses two 256MB DDR3-SDRAM ICs. This device operates at 1.5V voltage level. DDR3-SDRAM ICs are
physically located on top side of the SOM. The RAM size can be expandable up to maximum of 2GB. For customised
DDR3 memory based SOM contact iWave support team.
2.4.2 SPI NOR Flash
The RZ/G1E SODIMM SOM supports 16Mb SPI NOR Flash as default boot device. This is connected to QSPI controller
of the RZ/G1E CPU and operates at 3.3 Voltage level. While RZ/G1E booting, boot program in the on-chip ROM starts
up the QSPI and SYS-DMAC channel 1 and transfers the loader program previously stored in the SPI Flash to the on-
chip RAM via the QSPI controller. After loader program is transferred, the program automatically jumps to the top
address of the loader program. The SPI flash memory (U14) is physically located on bottom side of the SOM.
To program the boot code in to the SPI flash (for the first time or if boot code is corrupted), use iWave’s RZ/G1E SPI
Programmer Board through SPI Flash Programming Header (Example part: TMM-103-01-L-D). Optionally the external
SPI programmer can be used for programming the SPI flash through SPI Flash Programming Header (J2). Optionally
the JTAG Header, which is available on the RZ/G1E SODIMM carrier board can be used for programming the SPI
flash.
Figure 3: SPI Flash Progarming Header
Table 3: SPI Header
SI.No Pin Number Pin name
1 1 SPI_MISO
2 2 SPI_CS
3 3 SPI_MOSI
4 4 GND
5 5 VCC