iWave iW-RainboW-G22M, Hardware User'S Manual

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REL1.2
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RZ/G1E SODIMM SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.7.10 UART Interface
The RZ/G1E SODIMM SOM supports seven UART interfaces on SODIMM Edge connector in which one is for Debug
UART interface and other six for Data UART interface. The RZ/G1E CPU’s SCIF4 controller is used for Debug UART
interface and SCIF1, SCIF2, SCIF3, SCIF5, HSCIF1 and HSCIF2 controller is used for Data UART interface. Also, HSCIF1
and HSCIF2 interface supports hardware flow control for request to send and clear to send signals on SODIMM Edge
connector.
The RZ/G1E CPU’s SCIF module has two 16 -stage FIFO buffers separately for transmission and reception, which
enables fast, efficient, and uninterrupted full duplex communication. It has On-chip baud rate generator that allows
any bit rate to be selected. Also, it supports DMA transfers.
The RZ/G1E CPU’s HSCIF is a high-speed serial communication interface with built-in FIFO buffers that handles
asynchronous communication. It has two 128-stage FIFO buffers separately for transmission and reception, which
enables fast, efficient, and uninterrupted communication.
For more details, refer SODIMM Edge connector pins 94 & 97 for SCIF1, 52 & 53 for SCIF2, 56 & 57 for SCIF3, 117 &
118 for SCIF4, 7 & 9 for SCIF5, 38, 74, 75, 102 & 103 for HSCIF1 and 96, 98, 99, 100 & 101 for HSCIF2 on Table 6.
Note: Since HSCIF2 interface TXD and RXD signals are shared between Wi-Fi/BT module and SODIMM Edge pins,
either one only can be used at a time. By default, Wi-Fi/BT module pins are supported.
Note: Since SCIF5 interface is shared between Wi-Fi/BT module and SODIMM Edge pins, either one only can be used
at a time. By default, Edge pins are supported.
2.7.11 SPI Interface
The RZ/G1E SODIMM SOM supports three SPI interfaces on SODIMM Edge connector. RZ/G1E CPU’s MSIOF0 &
MSIOF1 with two chip selects and MSIOF2 with one chip select is used for SPI interface, which supports full-duplex
synchronous four-wire serial interface with DMA.
The RZ/G1E CPU’s MSIOF controller supports serial formats IIS, SPI (master and slave modes) at max speed of
26Mbps. It supports 32bit x 64 stages for transmit FIFOs & 32bit × 256 stages for receive FIFOs and allows MSB first
or LSB first selectable for data transmission and reception.
For more details, refer SODIMM Edge connector pins 68, 69, 73, 80 & 86 for MSIOF0, pins 47, 62, 63, 66, 70 & 71 for
MSIOF1 and 181, 189, 194 & 196 for MSIOF2 on Table 6.
Note: In RZ/G1E SODIMM SOM, VIN1 and MSIOF1 interface signals are connected to same pins of SODIMM Edge
connector (through isolating resistors) and so either one interface only can be used at a time.By default, VIN1 camera