Specifications
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Device Specifications
• 2 DSP s a nd 1 R ISC pro ce sso r fo r 88 MIP S o f pro ce ssing
• 1 MB m e ssa ge buffe r* P o we r C o nsum ptio n (typica l) : 100m A @ 14.4 VDC
• Sle e p P o we r C o nsum ptio n (typica l) : 8m A @ 12.0 VDC
• P o we r Supply: 5.5-32 Vo lt P o we r O pe ra tio n
• Te m pe ra ture R a nge : -40C to +85C
• Ve hicle C o nne cto rs : 15 P in m a le D-SUB
• Ge ne ra l P urpo se IO : 3 MISC IO (0 - 3.3V)
• Ge ne ra l P urpo se IO ra te re po rt inte rva l: 1 Hz to 10 Khz o r ba se d o n digita l cha nge
• Micro so ft© C e rtifie d USB drive rs
• Iso la te d USB 2.0 Full Spe e d De vice ba ck wa rd co m pa tible with USB1.1
• Sta nd-Alo ne Mo de Including Scripting, R e ce ive Me ssa ge s, Tra nsm it Me ssa ge s, Ex pre ssio ns, IO , a nd Tra nspo rt La ye rs
• R S232 ho st po rt with HW ha ndsha k ing suppo rt fo r scripting a nd ga te wa ying ne two rk da ta
• IC S T im e Sync fo r Multiple Ha rdwa re Synchro niza tio n suppo rts a ll ne o VI 3G de vice s
• J2534 a nd R P 1210 A/B co m pa tible fo r C AN/ISO 15765, J1708, Ke ywo rd, a nd ISO 9141
• m icro SD ca rd slo t suppo rt up to 12 Giga byte s o f sto ra ge . T he re m o va ble ca rd is fo rm a tte d using FAT 32 fo r dire ct usa ge in a P C .
• Ba tte ry ba ck e d re a l-tim e clo ck (R T C )
• Wa rra nty: O ne Ye a r Lim ite d Wa rra nty
• Firm wa re : Fie ld upgra de a ble de sign (fla sh firm wa re )
Networks - General
• 64 Bit tim e sta m ping to a ccura cy o f 10 m icro se co nds o n ne two rk s a nd ne ve r o ve rflo ws. 0.5 m icro se co nd a ccura cy tim e sta m p a va ila ble if using o ne ne two rk o nly
• Sim ulta ne o us o pe ra tio ns o n a ll ne two rk s
• Tra nsm it m e ssa ge do uble -buffe ring o n a ll ne two rk s a llo ws ba ck to ba ck m e ssa ge tra nsm issio n
Network Specifications
2x J1939/CA N Channels
• 2 De dica te d ISO 11898 Dua l W ire C AN P hysica l La ye r (T JA1040)
• C AN 2.0B Active
• Up to 1 M-Bit So ftwa re Se le cta ble Ba ud R a te (a uto ba ud ca pa ble )
• C a pa ble o f ge ne ra ting a nd de te cting e rro r fra m e s
• Lo gic Ana lysis o f C AN Wa ve fo rm with 25 na no se co nd re so lutio n
• Gra phica l Bit T im e / Ba ud R a te C a lcula to r
• Liste n o nly m o de suppo rt* Unte rm ina te d ne two rk de te ctio n
J1708
• High pre cisio n tim e ca pture o f J1708 bus e ve nts
• So ftwa re se le cta ble pa ra m e te rs including ba ud ra te
• SAE J1708 P hysica l la ye r
K and L Line, 1x LIN (Local Interconnect), ISO9141, or Keyword 2000
• UAR T Ba se d Sta te Ma chine
• Initia liza tio n Wa ve fo rm s including Fa st Init, Five Ba ud, a nd C usto m
• P ro gra m m a ble T im ing P a ra m e te rs including Inte r-Byte , T X Inte r-Fra m e , R X Inte r-Fra m e a nd Initia liza tio n Wa ve fo rm s (0.5 m s R e so lutio n) Full suppo rt fo r LIN 1.X, 2.X a nd J2602
• K a nd L ha ve so ftwa re co ntro lle d tra nsm it e na ble line s a llo wing m a ny diffe re nt va ria nts o f UAR T o r ISO 9141 co m m unica tio ns including:T x o n L R x o n K (full duple x );T x a nd R x o n K (ha lf duple x );T x o n K a nd L a nd R x o n K
• So ck e t se le cta ble pull up re sisto r o n bo th K a nd L line s
• C a pa ble o f Ge ne ra ting LIN Wa ve fo rm s (Including Erro rs) Using De dica te d O utput C o m pa re Ha rdwa re
• So ftwa re Se le cta ble Ba ud R a te
• LIN Bus Mo nito r Mo de ide ntifie s e rro rs : Sync Bre a k Erro r Sta te a nd Le ngth, Sync Wa ve Erro r, Me ssa ge ID pa rity, T Fra m e Ma x /Sla ve No t R e spo nding, C he ck sum Erro r a nd Tra nsm it Bit Erro rs.
• LIN Bus Ma ste r Mo de o pe ra te s a t sa m e tim e a s LIN Bus Mo nito r
• LIN Bus Sla ve sim ula tio n - with o r witho ut a n LDF file
• LIN Bus ha rdwa re sche dule ta ble with suppo rt fo r LIN dia gno stics GM C la ss 2/ SAE J1850 VP W
• VP W P hysica l La ye r ca pa ble o fT x a nd R x o pe ra tio ns in high spe e d m o de s (MC 33390)
• R e ce ptio n o f IFR da ta during rx a nd tx
• Lo ng Me ssa ge tra nsm it a nd re ce ptio n fo r EC U fla shing
neoVI Documentation - (C) Copyright 2000-2019 Intrepid Control Systems, Inc.
La st Upda te :
Tuesday, January 08, 2013
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Summary of Contents for neoVI
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