* So ftwa re se le cta ble ba ud ra te /bit tim ing up to lim ita tio ns o f physica l la ye r.
* Gra phica l Bit T im e /Ba ud R a te C a lcula to r
GM Class 2/ SA E J1850 VPW
* VP W P hysica l La ye r ca pa ble o f T x a nd R x o pe ra tio ns in high spe e d m o de s (MC 33390)
* So ftwa re co ntro lle d pe riphe ra l ba se d VP W ge ne ra tio n
* So ftwa re m o difia ble bit tim ing a cce pta nce pa ra m e te rs
* So ftwa re m o difia ble bit tim ing ge ne ra tio n pa ra m e te rs
* Trigge r ge ne ra tio n ba se d o n ne two rk e rro r o r lo st a rbitra tio n e ve nt
* Ba d C R C ge ne ra tio n
* 4x high spe e d m o de (lim ite d sim ulta ne o us o pe ra tio ns a t 41.6 k-bits)
* Blo ck tra nsfe r m o de
* Bre a k ge ne ra tio n
* Ba d Me ssa ge ge ne ra tio n ca pa ble
UA RT/ISO9141/Keyword 2000 (ISO14230)
* K a nd L line s im ple m e nte d
* UAR T Ba se d sta te m a chine
* Initia liza tio n wa ve fo rm s including Fa st Init, Five Ba ud, C AR B a nd C usto m
* P ro gra m m a ble tim ing pa ra m e te rs including inte r-byte , T X inte r-fra m e , R X inte r-fra m e a nd initia liza tio n wa ve fo rm s (0.5 m s re so lutio n)
* So ftwa re se le cta ble ba ud ra te
* So ck e t se le cta ble pull up re sisto r o n bo th K a nd L line s
* Jum pe r se le cta ble pull up vo lta ge e ithe r 5V o r Ba tte ry
* K a nd L ha ve so ftwa re co ntro lle d tra nsm it e na ble line s a llo wing m a ny diffe re nt va ria nts o f UAR T o r ISO 9141 co m m unica tio ns including: T x o n L R x o n K; T x a nd R x o n K; T x o n K a nd L a nd R x o n K
Ford SCP/ SA E J1850 PWM
* Dua l BC C De sign : LBC C C o m m unica tio ns P ro to co l IC T x /R x with o ptio na l "Mo nito r Mo de " pe rfo rm e d by a a dditio na l pro ce sso r
* So ftwa re se tup o f LBC C including the No de Addre ss, Lo o k up Ta ble 1 a nd 2, a nd the Ne two rk Drive r a nd R e ce ive C o ntro l R e giste r
* So ftwa re se le cta ble SC P bit ra te o f 41.6 k bps o r 83.3 k bps
* Dyna m ic No de Addre ss m o de : LBC C is re co nfigure d whe n a m e ssa ge to be tra nsm itte d ha s a diffe re nt no de a ddre ss the n pre vio usly co nfigure d
SA E J1708
* SAE J1708 P hysica l La ye r
* So ftwa re se tup o f SAE J1708 pa ra m e te rs
neoVI Documentation - (C) Copyright 2000-2019 Intrepid Control Systems, Inc.
La st Upda te :
Wednesday, June 04, 2014
Intrepid Hardware Help
Specifications
49 / 71
Summary of Contents for neoVI
Page 60: ...Last Update Friday September 13 2013 Intrepid Hardware Help LED Blinking 58 71 ...
Page 63: ...Last Update Tuesday January 08 2013 Intrepid Hardware Help General Purpose IO 61 71 ...
Page 67: ...Intrepid Hardware Help General Purpose IO 65 71 ...
