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VGA Frame Buffer USWC
Set this option to Enabled to enable the VGA video frame buffer using USWC (Uncacheable,
Speculatable, Write-Combined) memory. The settings are Enabled or Disabled. Older ISA
VGA card drivers may not behave correctly if this option is not set to Disabled. The Optimal
and Fail-Safe settings are Disabled.
PCI Frame Buffer USWC
Set this option to Enabled to enable the USWC memory attribute and improve video
performance when a PCI video adapter is installed. However, VGA card drivers may not
behave correctly when this option is set to Enabled. The settings are Disabled or Enabled.
The Optimal and Fail-Safe settings are Disabled.
Fixed Memory Hole
This option specifies the location of an area of memory that cannot be addressed on the ISA
bus. The settings are Disabled, 15 MB-16 MB, or 512 KB-640 KB. The Optimal and Fail-
Safe settings are Disabled.
CPU To IDE Posting
Set this option to Enabled to allow the processor to post writes from the processor to the IDE
controller. The settings are Enabled or Disabled. The Optimal and Fail-Safe settings are
Enabled.
USWC Write Posting
Set this option to Enabled to allow write operations from USWC memory to be posted. The
settings are Enabled or Disabled. The Optimal and Fail-Safe settings are Enabled.
CPU To PCI Posting
Set this option to Enabled to allow write operations from the processor to be posted to the
PCI bus. The settings are Enabled or Disabled. The Optimal and Fail-Safe settings are
Enabled.
PCI To DRAM Pipeline
Set this option to Enabled to enable the pipeline from the PCI bus to DRAM system memory.
The settings are Enabled or Disabled. The Optimal and Fail-Safe settings are Enabled.
